CY3682(2004) Просмотр технического описания (PDF) - Cypress Semiconductor
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CY3682 Datasheet PDF : 42 Pages
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FO R
FO R
CY7C68001
7.6 EPxPKTLENH/L Registers 0x0A–0x11
The external master can use these registers to set smaller
packet sizes than the physical buffer size (refer to the previ-
ously described EPxCFG registers). The default packet size is
512 bytes for all endpoints. Note that EP2 and EP6 can have
maximum sizes of 1024 bytes, and EP4 and EP8 can have
maximum sizes of 512 bytes, to be consistent with the
endpoint structure.
In addition, the EPxPKTLENH register has four other endpoint
configuration bits.
EPxPKTLENL
0x0B, 0x0D,
0x0F, 0x11
Bit #
7
6
5
4
3
2
1
0
Bit Name PL7 PL6 PL5 PL4 PL3 PL2 PL1 PL0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default
0
0
0
0
0
0
0
0
EP2PKTLENH,
EP6PKTLENH
Bit #
7
6
5
4
3
Bit Name INFM1 OEP1 ZERO WORD 0
LEN WIDE
Read/Write R/W R/W R/W R/W R/W
Default
0
0
1
1
0
2
PL10
R/W
0
0x0A, 0x0E
1
0
PL9 PL8
R/W R/W
1
0
EP4PKTLENH,
EP8PKTLENH
0x0C, 0x10
Bit #
7
6
5
4
3
2
1
0
Bit Name INFM1 OEP1 ZERO WORD 0
LEN WIDE
0 PL9 PL8
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default
0
0
1
1
0
0
1
0
7.6.1 Bit 7: INFM1 EPxPKTLENH.7
When the external master sets INFM = 1 in an endpoint config-
uration register, the FIFO flags for that endpoint become valid
one sample earlier than when the full condition occurs. These
bits take effect only when the FIFOs are operating synchro-
nously according to an internally or externally supplied clock.
Having the FIFO flag indications one sample early simplifies
some synchronous interfaces. This applies only to IN
endpoints. Default is INFM1 = 0.
7.6.2 Bit 6: OEP1 EPxPKTLENH.6
When the external master sets an OEP = 1 in an endpoint
configuration register, the FIFO flags for that endpoint become
valid one sample earlier than when the empty condition
occurs. These bits take effect only when the FIFOs are
operating synchronously according to an internally or exter-
nally supplied clock. Having the FIFO flag indications one
sample early simplifies some synchronous interfaces. This
applies only to OUT endpoints. Default is OEP1 = 0.
7.6.3 Bit 5: ZEROLEN EPxPKTLENH.5
When ZEROLEN = 1 (default), a zero length packet will be
sent when the PKTEND pin is asserted and there are no bytes
in the current packet. If ZEROLEN = 0, then a zero length
packet will not be sent under these conditions.
7.6.4 Bit 4: WORDWIDE EPxPKTLENH.4
This bit controls whether the data interface is 8 or 16 bits wide.
If WORDWIDE = 0, the data interface is eight bits wide, and
FD[15:8] have no function. If WORDWIDE = 1 (default), the
data interface is 16 bits wide.
7.6.5 Bit [2..0]: PL[X:0] Packet Length Bits
The default packet size is 512 bytes for all endpoints.
7.7 EPxPFH/L Registers 0x12–0x19
The Programmable Flag registers control when the PF goes
active for each of the four endpoint FIFOs: EP2, EP4, EP6,
and EP8. The EPxPFH/L fields are interpreted differently for
the high speed operation and full speed operation and for OUT
and IN endpoints.
Following is the register bit definition for high speed operation
and for full speed operation (when endpoint is configured as
an isochronous endpoint).
Full Speed ISO and High Speed Mode: EP2PFL,
EP4PFL, EP6PFL, EP8PFL
0x13, 0x15,
0x17, 0x19
Bit #
7
6
5
4
3
2
1
0
Bit Name PFC7 PFC6 PFC5 PFC4 PFC3 PFC2 PFC1 PFC0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default
0
0
0
0
0
0
0
0
Full Speed ISO and High Speed Mode:
EP4PFH, EP8PFH
0x14, 0x18
Bit #
7
6
5
4
3
21 0
Bit Name
DECIS PKTSTAT 0 IN:
IN: 0
PKTS[1] PKTS[0]
OUT: OUT:
PFC10 PFC9
0 PFC8
Read/Write R/W
R/W R/W R/W R/W R/W R/W R/W
Default
0
0
0
0
1
00 0
Full Speed ISO and High Speed Mode:
EP2PFH, EP6PFH
0x12, 0x16
Bit #
7
6
5
4
3
21 0
Bit Name
DECIS PKTSTAT IN:
IN:
IN: 0 PFC9 PFC8
PKTS[2] PKTS[1] PKTS[0]
OUT: OUT: OUT:
PFC12 PFC11 PFC10
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default
1
0
0
0
1
00 0
Following is the bit definition for the same register when the
device is operating at full speed and the endpoint is not
configured as isochronous endpoint.
Full Speed Non-ISO Mode: EP2PFL,
EP4PFL, EP6PFL, EP8PFL
0x13, 0x15,
0x17, 0x19
Bit #
7
6
5
4
3
2
1
0
Bit Name
IN:
IN: PFC5 PFC4 PFC3 PFC2 PFC1 PFC0
PKTS[1] PKTS[0]
OUT: OUT:
PFC7 PFC6
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Default
0
0
0
0
0
0
0
0
Document #: 38-08013 Rev. *E
Page 18 of 42
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