CY3682(2004) Просмотр технического описания (PDF) - Cypress Semiconductor

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CY3682
(Rev.:2004)

High-Speed USB Interface Device

Cypress Semiconductor 

FO R

FO R

CY7C68001

6.3 CY7C68001 Pin Definitions

Table 6-1. SX2 Pin Definitions

QFN SSOP

Pin Pin Name

Type

3 10 AVCC Power

6 13 AGND Power

9 16 DMINUS I/O/Z

8 15 DPLUS I/O/Z

42 49 RESET# Input

5 12 XTALIN Input

4 11 XTALOUT Output

54 5

NC

Output

Default

Description

N/A Analog VCC. This signal provides power to the analog section of the chip.

N/A Analog Ground. Connect to ground with as short a path as possible.

Z USB D– Signal. Connect to the USB D– signal.

Z USB D+ Signal. Connect to the USB D+ signal.

N/A Active LOW Reset. Resets the entire chip. This pin is normally tied to VCC

through a 100K resistor, and to GND through a 0.1-µF capacitor.

N/A Crystal Input. Connect this signal to a 24-MHz parallel-resonant, fundamental

mode crystal and 20-pF capacitor to GND. It is also correct to drive XTALIN with

an external 24-MHz square wave derived from another clock source.

N/A Crystal Output. Connect this signal to a 24-MHz parallel-resonant, fundamental

mode crystal and 20-pF capacitor to GND. If an external clock is used to drive

XTALIN, leave this pin open.

O No Connect. This pin must be left unconnected.

33 40 READY Output

L READY is an output-only ready that gates external command reads and writes.

Active High.

34 41

INT#

Output

H INT# is an output-only external interrupt signal. Active Low.

35 42 SLOE

Input

I SLOE is an input-only output enable with programmable polarity (POLAR.4) for

the slave FIFOs connected to FD[7:0] or FD[15:0].

36 43 FIFOADR2 Input

I FIFOADR2 is an input-only address select for the slave FIFOs connected to

FD[7:0] or FD[15:0].

37 44 FIFOADR0 Input

I FIFOADR0 is an input-only address select for the slave FIFOs connected to

FD[7:0] or FD[15:0].

38 45 FIFOADR1 Input

I FIFOADR1 is an input-only address select for the slave FIFOs connected to

FD[7:0] or FD[15:0].

39 46 PKTEND Input

I PKTEND is an input-only packet end with programmable polarity (POLAR.5) for

the slave FIFOs connected to FD[7:0] or FD[15:0].

40 47 FLAGD/C CS#:I

I FLAGD is a programmable slave-FIFO output status flag signal. CS# is a master

S# FLAGD:O

chip select (default).

18 25

FD[0]

I/O/Z

I FD[0] is the bidirectional FIFO/Command data bus.

19 26

FD[1]

I/O/Z

I FD[1] is the bidirectional FIFO/Command data bus.

20 27

FD[2]

I/O/Z

I FD[2] is the bidirectional FIFO/Command data bus.

21 28

FD[3]

I/O/Z

I FD[3] is the bidirectional FIFO/Command data bus.

22 29

FD[4]

I/O/Z

I FD[4] is the bidirectional FIFO/Command data bus.

23 30

FD[5]

I/O/Z

I FD[5] is the bidirectional FIFO/Command data bus.

24 31

FD[6]

I/O/Z

I FD[6] is the bidirectional FIFO/Command data bus.

25 32

FD[7]

I/O/Z

I FD[7] is the bidirectional FIFO/Command data bus.

45 52

FD[8]

I/O/Z

I FD[8] is the bidirectional FIFO data bus.

46 53

FD[9]

I/O/Z

I FD[9] is the bidirectional FIFO data bus.

47 54 FD[10] I/O/Z

I FD[10] is the bidirectional FIFO data bus.

48 55

FD[11]

I/O/Z

I FD[11] is the bidirectional FIFO data bus.

49 56 FD[12] I/O/Z

I FD[12] is the bidirectional FIFO data bus.

50 1

FD[13]

I/O/Z

I FD[13] is the bidirectional FIFO data bus.

51 2

FD[14]

I/O/Z

I FD[14] is the bidirectional FIFO data bus.

52 3

FD[15]

I/O/Z

I FD[15] is the bidirectional FIFO data bus.

Document #: 38-08013 Rev. *E

Page 12 of 42

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