KE5B256B1CFP Просмотр технического описания (PDF) - KAWASAKI MICROELECTRONICS

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KE5B256B1CFP

ADDRESS PROCESSOR

KAWASAKI MICROELECTRONICS 

1. Features

1.1 Introduction

1.2 Functional Overview

1.3 Specifications

1.4 Register Names

2. Block Diagram

Table of Contents

Address Processor KE5B256B1

8. CPU Port

8.1 Access to Registers

8.2 Basic Operation through CPU Port

8.3 Search Operation through CPU Port

8.4 Search Result Output from CPU Port

8.5 HHA/HEA Register Operation

8.6 Automatic Increment Function

8.7 Table Maintenance

3. Pin Assignment and Pin Descriptions

3.1 Pin Assignment

3.2 Pin Descriptions

4. Port and Operation Mode Overview

4.1 Port Overview

4.2 Arbitration

4.3 Operation Modes Overview

4.4 External Arbitration

9. Cascading

9.1 Device ID Registration

9.2 Priority

9.3 Cascade Connection

9.4 Input Port in a Cascade System

9.5 Output Port in a Cascade System

9.6 CPU Port in a Cascade System

9.7 AC Characteristics in a Cascade System

9.8 Single Device Operation

5. CAM Table

5.1 Entry and Segment

5.2 Table Configuration

5.3 Read/Write Segment Data

5.4 Search and CAM Table

6. Input Port

6.1 Input Port Configuration

6.2 IP Sequence Configuration

6.3 Selection of Channel and Start Sequence Num-

ber

6.4 IP Sequence Operation

6.5 HHA Automatic Output

7. Output Port

7.1 OP Sequence Configuration

7.2 Selection of Channel and Start Sequence Num-

ber

7.3 OP Sequence Operation

10. Initialization

11. Examples

12. Command Descriptions

12.1 Command Functions

12.2 Conditions for Executing Commands

13. Register Descriptions

13.1 Overview

13.2 Register Addresses

13.3 Register Bit Maps

13.4 Conditions for Accessing Registers

14. Electrical Characteristics

14.1 Absolute Maximum Ratings

14.2 Operating Range

14.3 DC Characteristics

14.4 AC Characteristics

15. Package Outline

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