KE5B256B1CFP Просмотр технического описания (PDF) - KAWASAKI MICROELECTRONICS

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KE5B256B1CFP

ADDRESS PROCESSOR

KAWASAKI MICROELECTRONICS 

3.2 Pin Descriptions

Pin name

DAT<15:0>

ADD<7:0>

CE_

Attribute

CPU Port Data Bus

Input / Output

Tri-state LVTTL

CPU Port Address

Bus

Input

LVTTL

Device Enable

Input

LVTTL

Address Processor KE5B256B1

Function

DAT<15:0> is a 16-bit, bidirectional data bus used to con-

vey data, commands, and status to and from the Address

Processor (AP). The direction is controlled by the state of

R/W_. DAT<15:0> is enabled by a low level of CE_.

ADD<7:0> is an 8-bit address bus used to select registers.

CE_ is used for access from the CPU Port. R/W_,

ADD, DAT inputs are latched on the falling edge of CE_.

R/W_

Read/Write

Input

LVTTL

R/W_ low selects a write cycle. R/W_ high selects a read

cycle. The state of R/W_ is registered on the falling edge of

CE_.

RST_

ID<31:0>

Hardware Reset

Input

LVTTL

RST_ is a hardware reset signal. A low pulse of RST_ ini-

tializes the AP. The minimum low hold time is 40ns.

Input Port

Data Bus

Input

LVTTL

ID<31:0> is a 32-bit data bus used to convey search data to

the AP through the Input Port. The ID bus width can also

be configured to 8 bits (ID<7:0>) or 16 bits (ID<15:0>).

3-4

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