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FX909AD2

Wireless Modem Data Pump

CML Microsystems Plc 

Wireless Modem Data Pump

FX909A

Command Register B7: AQBC - Acquire Bit Clock

This bit has no effect in transmit mode.

In receive mode, whenever a byte with the AQBC bit set to '1' is written to the Command Register,

and TASK is not set to RESET, it initiates an automatic sequence designed to achieve bit timing

synchronisation with the received signal as quickly as possible. This involves setting the Phase

Locked Loop of the received bit timing extraction circuits to its widest bandwidth, then gradually

reducing the bandwidth as timing synchronisation is achieved, until it reaches the 'normal' value set

by the PLLBW bits of the Control Register.

Setting this bit to '0' (or changing it from '1' to '0') has no effect, however note that the acquisition

sequence will be re-started every time that a byte written to the Command Register has the AQBC bit

set to '1'.

The AQBC bit will normally be set up to 12 bits before an SFS (Search for Frame Sync) or SFH

(Search for Frame Head) task, however it may also be used independently to re-establish clock

synchronisation quickly after a long fade. Alternatively, a SFS or SFH task may be written to the

Command Register with the AQBC bit '0' if it is known that clock synchronisation does not need to be

re-established. More details of the bit clock acquisition sequence are given in section 1.6.3.

Command Register B6: AQLEV - Acquire Receive Signal Levels

This bit has no effect in transmit mode.

In receive mode, whenever a byte with the AQLEV bit set to '1' is written to the Command Register

and TASK is not set to RESET, it initiates an automatic sequence designed to measure the amplitude

and dc offset of the received signal as rapidly as possible. This sequence involves setting the

measurement circuits to respond quickly at first, then gradually increasing their response time, hence

improving the measurement accuracy, until the 'normal' value set by the LEVRES bits of the Control

Register is reached.

Setting this bit to '0' (or changing it from '1' to '0') has no effect, however note that the acquisition

sequence will be re-started every time that a byte written to the Command Register has the AQLEV

bit set to '1'.

The AQLEV bit will normally be set up to 12 bits before an SFS (Search for Frame Sync) or SFH

(Search for Frame Head) task is initiated, however it may also be used independently to re-establish

signal levels quickly after a long fade. Alternatively, a SFS or SFH task may be written to the

Command Register with the AQLEV bit at '0' if it is known that there is no need to re-establish the

received signal levels. More details of the level measurement acquisition sequence are given in

section 1.6.3.

The error rate is highest immediately after a AQBC and AQLEV sequence is triggered and rapidly

reduces to its static value soon after. These erroneous bits could incorrectly trigger the frame sync

detection circuits and so it is suggested that a SFH or SFS task is set 12 bits after setting either of

the AQLEV or AQBC sequences.

Command Register B5, B4, B3

These bits should be set to '0'.

Command Register B2, B1, B0: TASK - Task

Operations such as transmitting a data block are treated by the modem as 'tasks' and are initiated

when the µC writes a byte to the Command Register with the TASK bits set to anything other than

the 'NULL' code.

© 1996 Consumer Microcircuits Limited

14

D/909A/4

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