Wireless Modem Data Pump
FX909A
Figure 10 Receive Mode Timing Diagram
t3 Time to receive all bits of task
t6 Maximum time between first bit of task
entering de-interleave circuit and task
being written to modem.
t7 Time from last bit of task entering de-interleave
circuit to BFREE going to a logic '1' (high)
Task
SFH
R3H
RDB
RSB
SFH
R3H
RDB
RSB
Any
Typical time
(bit-times)
56
24
240
8
14
18
218
6
1
© 1996 Consumer Microcircuits Limited
21
D/909A/4