s MSM7712 s –––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––––
SCK, RCK, PCLK Timing
SCK, RCK, PCLK Timing
Symbol
Tskl
Tskh
Td (prck-sck)
Min.
Typ.
12.5
16.625
12.5
16.625
0
10
Max.
-
-
20
Notes (RCK at 16 MHz
System Clock low time
System Clock high time
Delay time from SCK rising edge to PCLK and SCK changing state
tSKI
SCK
tSKH
RCK, PCK (1)
tD(PRCK-SCK)
PCLK (2)
tD(PRCK-SCK)
Note: PCLK (1) when PCLK_DIV = 2, 4, or 8.
PCLK (2) when PCLK_DIV = 1.
Figure 12. SCK, RCK, PCK Timing
20
Oki Semiconductor