DS2180A Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated
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DS2180A Datasheet PDF : 35 Pages
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DS2180A
TRANSMIT PIN DESCRIPTION (40-PIN DIP ONLY) Table 1
PIN SYMBOL TYPE
DESCRIPTION
1
TMSYNC
I
Transmit Multiframe Sync. May be pulsed high at multiframe boundaries to
reinforce multiframe alignment or tied low, which allows internal multiframe
counter to free run.
2
TFSYNC
I
Transmit Frame Sync. Rising edge identifies frame boundary; may be pulsed
every frame to reinforce internal frame counter or tied low (allowing TMSYNC to
establish frame and multiframe alignment).
3
TCLK
I
Transmit Clock. 1.544 MHz primary clock.
4
TCHCLK
O
Transmit Channel Clock. 192 kHz clock which identifies time slot (channel)
boundaries. Useful for parallel-to-serial conversion of channel data.
5
TSER
I
Transmit Serial Data. NRZ data input, sample on falling edge of TCLK.
6
TMO
O
Transmit Multiframe Out. Output of internal multiframe counter indicates
multiframe boundaries. 50% duty cycle.
7
TSIGSEL
O
Transmit Signaling Select. .667 kHz clock which identifies signaling frame A and
C in 193E framing. 1.33 kHz clock in 193S.
8
TSIGFR
O
Transmit Signaling Frame. High during signaling frames, low otherwise.
9
TABCD
I
Transmit ABCD Signaling. When enabled via TCR.4, sampled during channel
LSB time in signaling frames on falling edge of TCLK.
10
TLINK
I
Transmit Link Data. Sampled during the F-bit time (falling edge of TCLK) of odd
frames for insertion into the outgoing data stream (193E-FDL insertion). Sampled
during the F-bit time of even frames for insertion into the outgoing data (193S-
External S-Bit insertion).
11
TLCLK
O
Transmit Link Clock. 4 kHz demand clock for TLINK input.
12
TPOS
O
Transmit Bipolar Data Outputs. Updated on rising edge of TCLK.
13
TNEG
PORT PIN DESCRIPTION (40-PIN DIP ONLY) Table 2
PIN SYMBOL TYPE
DESCRIPTION
14
INT 1
O
Receive Alarm Interrupt. Flags host controller during alarm conditions. Active
low, open drain output.
15
SDI1
16
SDO1
I
Serial Data In. Data for onboard registers. Sampled on rising edge of SCLK.
O
Serial Data Out. Control and status information from onboard registers. Updated
on falling edge of SCLK, tri-stated during serial port write or when CS is high.
17
CS 1
18
SCLK1
19
SPS
I
Chip Select. Must be low to write or read the serial port registers.
I
Serial Data Clock. Used to write or read the serial port registers.
I
Serial Port Select. Tie to VDD to select serial port. Tie to VSS to select hardware
mode.
NOTE:
1. Multifunction pins. See “Hardware Mode Description."
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