DS2180A Просмотр технического описания (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS2180A

T1 Transceiver

Dallas Semiconductor -> Maxim Integrated 

DS2180A

All data transfers are terminated if the CS input transitions high. Port control logic is disabled and SDO is

tri-stated when CS is high.

DATA I/O

Following the eight SCLK cycles that input an address/ command byte to write, a data byte is strobed into

the addressed register on the rising edges of the next eight SCLK cycles. Following an address/command

word to read, contents of the selected register are output on the falling edges of the next eight SCLK

cycles. The SDO pin is tri-stated during device write and may be tied to SDI in applications where the

host processor has a bi-directional I/O pin.

BURST MODE

The burst mode allows all onboard registers to be consecutively read and written by the host processor. A

burst read is used to poll all registers; RSR contents will be unaffected. This feature minimizes device

initialization time on power-up or system reset. Burst mode is initiated when ACB.7 is set and the address

nibble is 0000. Burst is terminated by a low-high transition on CS .

ACB: ADDRESS COMMAND BYTE Figure 2

(MSB)

BM

-

-

ADD3

ADD2

ADD1

(LSB)

AD0

R/ W

SYMBOL

BM

-

-

ADD3

ADD0

R/ W

POSITION

ACB.7

ACB.6

ACB.5

ACB.4

ACB.1

ACB.0

NAME AND DESCRIPTION

Burst Mode. If set (and ACB.1 through ACB.4=0) burst read or

write is enabled.

Reserved, must be 0 for proper operation.

Reserved, must be 0 for proper operation.

MSB of register address.

LSB of register address.

Read/Write Select.

0 = write addressed register.

1 = read addressed register.

SERIAL PORT READ/WRITE Figure 3

NOTES:

1. SDI sampled on rising edge of SCLK.

2. SDO updated on falling edge of SCLK.

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