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82378ZB

82378ZB SYSTEM I/O (SIO) AND 82379AB SYSTEM I/O APIC (SIO.A)

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82378ZB (SIO) AND 82379AB (SIO.A)

E

Signal Name Type

Description

EOP

I/O

(82378ZB)

END OF PROCESS: EOP is bi-directional, acting in one of two modes, and is

directly connected to the TC line of the ISA Bus. DMA slaves assert EOP to the

SIO/SIO.A to terminate DMA cycles. The SIO/SIO.A asserts EOP to DMA slaves

as a terminal count indicator.

EOP-IN MODE: For all transfer types during DMA, the SIO/SIO.A samples EOP. If

it is sampled asserted, the transfer is terminated.

TC-OUT MODE: The SIO asserts EOP after a new address has been output, if the

byte count expires with that transfer. The EOP (TC) remains asserted until AEN is

negated, unless AEN is negated during an autoinitialization. EOP (TC) is negated

before AEN is negated during an autoinitialization.

When all the DMA channels are not in use, the EOP signal is in output mode and

negated (low). After PCIRST#, EOP is in output mode and inactive.

TC

O

(82379AB)

TERMINAL COUNT: The SIO.A asserts TC after a new address has been output, if

the byte count expires with that transfer. TC remains asserted until AEN is negated,

unless AEN is negated during an autoinitialization. TC is negated before AEN is

negated during an autoinitialization. After PCIRST#, EOP is in output mode and

inactive.

REFRESH# I/O

REFRESH: As an output, REFRESH# is used by the SIO/SIO.A to indicate when a

refresh cycle is in progress. It should be used to enable the SA[15:0] address to the

row address inputs of all banks of dynamic memory on the ISA Bus. Thus, when

MEMR# is asserted, the entire expansion bus dynamic memory is refreshed.

Memory slaves must not drive any data onto the bus during refresh. As an output,

this signal is driven directly onto the ISA Bus. This signal is an output only when the

SIO/SIO.A DMA refresh is a master on the bus responding to an internally

generated request for refresh.

As an input, REFRESH# is driven by 16-bit ISA Bus masters to initiate refresh

cycles. Upon PCIRST#, this signal is tri-stated.

2.7. Timer Signal

Signal Name Type

Description

SPKR

O

(82378ZB)

SPEAKER DRIVE: The SPKR signal, in the 82378ZB and 82379AB, is the output of

counter 2 and has a 24 mA drive capability. Upon reset, its output state is 0.

SPKR/TESTO

(82379AB)

For the 82379AB in test mode, this pin is the output pin used during NAND tree

testing.

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