82378ZB Просмотр технического описания (PDF) - Intel

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82378ZB

82378ZB SYSTEM I/O (SIO) AND 82379AB SYSTEM I/O APIC (SIO.A)

Intel 

E

82378ZB (SIO) AND 82379 (SIO.A)

Signal Name Type

Description

CPUGNT# t/s/o CPU GRANT: If the SIO/SIO.A internal arbiter is enabled, this pin is configured as

CPUGNT#. The SIO/SIO.A internal arbiter asserts CPUGNT# to indicate that the

CPU initiator has been granted the PCI Bus. If the internal arbiter is disabled, this

signal is meaningless. CPUGNT# is tri-stated from the leading edge of PCIRST#.

CPUGNT# is tri-stated until driven by the SIO/SIO.A. CPUGNT# is driven based on

the arbitration scheme and the asserted REQx#s.

GNT0#/

SIOREQ#

t/s/o GRANT 0/SIO REQUEST: If the SIO/SIO.A internal arbiter is enabled, this pin is

configured as GNT0#. The SIO/SIO.A internal arbiter asserts GNT0# to indicate

that Initiator0 has been granted the PCI Bus. If the internal arbiter is disabled, this

pin is configured as SIOREQ#. The SIO/SIO.A asserts SIOREQ# to request the

PCI Bus. GNT0#/SIOREQ# is tri-stated from the leading edge of PCIRST#.

GNT0#/SIOREQ# is tri-stated until driven by the SIO/SIO.A. GNT0#/SIOREQ# is

driven based on the arbitration scheme and the asserted REQx#'s.

GNT1#/

t/s/o GRANT 1/RESUME: If the SIO's internal arbiter is enabled, this pin is configured as

RESUME#

GNT1#. The SIO/SIO.A internal arbiter asserts GNT1# to indicate that Initiator1 has

been granted the PCI Bus. If the internal arbiter is disabled, this pin is configured as

RESUME#. The SIO/SIO.A asserts RESUME# to indicate that the conditions

causing the SIO/SIO.A to retry the cycle has passed. GNT1#/RESUME# is tri-

stated from the leading edge of PCIRST#. GNT1#/RESUME# is tri-stated until

driven by the SIO/SIO.A. GNT1#/RESUME# is driven based on the arbitration

scheme and the asserted REQx#'s.

REQ2#

I

REQUEST 2: This pin is an active low signal that indicates that Initiator2 desires the

use of the PCI Bus. This signal has a weak internal pull-up resistor.

REQ3#

I

REQUEST 3: This pin is an active low signal that indicates that Initiator3 desires the

use of the PCI Bus. This signal has a weak internal pull-up resistor.

GNT2#

t/s/o GRANT 2: This pin is configured as GNT2#. The SIO/SIO.A internal arbiter asserts

GNT2# to indicate that Initiator2 has been granted the PCI Bus. GNT2# is high upon

reset.

GNT3#

t/s/o GRANT 3: This pin is configured as GNT3#. The SIO/SIO.A internal arbiter asserts

GNT3# to indicate that Initiator3 has been granted the PCI Bus. GNT3# is high upon

reset.

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