82378ZB Просмотр технического описания (PDF) - Intel
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82378ZB Datasheet PDF : 137 Pages
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82378ZB (SIO) AND 82379 (SIO.A)
Signal Name Type
Description
SMEMW#
O
SYSTEM MEMORY WRITE: The SIO/SIO.A asserts SMEMW# to request a
memory slave to accept data from the data lines. If the access is below the 1 Mbyte
range (00000000−000FFFFFh) during DMA compatible, SIO/SIO.A master, or ISA
master cycles, the SIO/SIO.A asserts SMEMW#. SMEMW# is a delayed version of
MEMW#. SMEMW# is driven high upon reset.
SMEMR#
O
SYSTEM MEMORY READ: The SIO/SIO.A asserts SMEMR# to request a memory
slave to accept data from the data lines. If the access is below the 1 Mbyte range
(00000000−000FFFFFh) during DMA compatible, SIO/SIO.A master, or ISA master
cycles, the SIO/SIO.A asserts SMEMR#. SMEMR# is a delay version of MEMR#.
Upon PCIRST# this signal is low. SMEMR# is driven high upon reset.
ZEROWS# I
ZERO WAIT STATES: An ISA slave asserts ZEROWS# after its address and
command signals have been decoded to indicate that the current cycle can be
shortened. A 16-bit ISA memory cycle can be reduced to two SYSCLKs. An 8-bit
memory or I/O cycle can be reduced to three SYSCLKs. ZEROWS# has no effect
during 16-bit I/O cycles.
If IOCHRDY and ZEROWS# are both asserted during the same clock, then
ZEROWS# is ignored and wait states are added as a function of IOCHRDY (i.e.,
IOCHRDY has precedence over ZEROWS#).
OSC
I
OSCILLATOR: OSC is the 14.31818 MHz ISA clock signal. It is used by the
internal 8254 Timer, counters 0, 1, and 2.
RSTDRV
O
RESET DRIVE: The SIO/SIO.A asserts RSTDRV to reset devices that reside on
the ISA Bus. The SIO/SIO.A asserts this signal when PCIRST# (PCI Reset) is
asserted. In addition, the SIO/SIO.A can be programmed to assert RSTDRV by
writing to the ISA Clock Divisor Register. Software should assert the RSTDRV
during configuration to reset the ISA Bus when changing the clock divisor. Note that
when RSTDRV is generated via the ISA Clock Divisor Register, software must
ensure that RSTDRV is driven active for a minimum of 1 µs.
SD[15:0]
I/O
SYSTEM DATA: SD[15:0] provide the 16-bit data path for devices residing on the
ISA Bus. SD[15:8] correspond to the high order byte and SD[7:0] correspond to the
low order byte. SD[15:0] are undefined during refresh. The SIO/SIO.A tri-states
SD[15:0] during reset.
2.6. DMA Signals
Signal Name Type
Description
DREQ
I
[3:0,7:5]
DMA REQUEST: The DREQ lines are used to request DMA service from the
SIO/SIO.A DMA controller or for a 16-bit master to gain control of the ISA expansion
bus. The active level (high or low) is programmed via the DMA Command Register
(bit 6). The request must remain active until the appropriate DACK signal is
asserted.
DACK#
O
DMA ACKNOWLEDGE: The DACK output lines indicate that a request for DMA
[3:0,7:5]
service has been granted by the SIO/SIO.A or that a 16-bit master has been
granted the bus. The active level (high or low) is programmed via the DMA
Command Register (bit 7). These lines should be used to decode the DMA slave
device with the IOR# or IOW# line to indicate selection. Upon PCIRST#, these lines
are set inactive (high).
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