MTL003 Просмотр технического описания (PDF) - Myson Century Inc

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производитель

MTL003

SXGA Flat Panel Controller

Myson Century Inc 

MYSON

TECHNOLOGY

MTL003

(Rev. 0.95)

AD[7:0]

ADDRESS

DATA

ALE

HWR/HRD

Fig. 3.5.7 Direct Bus Timing

3.5.3 Interrupt

MTL003 supports one interrupt output signal (IRQ) which can be programmed to provide SYNC related or

function status related interrupts to the system. Upon receiving the interrupt request, Firmware needs to

firstly check the interrupt event by reading the Interrupt Flag Control registers (Reg. E8h and E9h) to decide

what events are happening. After the operation is completed, Firmware needs to clear interrupt status by

writing the same registers Reg. E8h and E9h. Furthermore, by using the Interrupt Flag Enable registers (Reg.

EAh and EBh), each interrupt event can be masked.

3.5.4 Screen Write

Screen Write function can be used to clear frame buffer memory and display output by a fixed value defined

in Reg. C6h, C7h, C8h.

3.5.5 Bi-directional GPIO

MTL003 supports eight General Purpose Input and Output (GPIO) pins GPIO[7:0] on chip. The GPIO[5:0]

pins are bi-directional GPIO pins, and the GPIO[7:6] pins are output only GPIO pins. There are two functions

for GPIO[7:6] pins. One is to set them as output only GPIO pins, and the other is to set them as Composite

decoded VSYNC/HSYNC for A/D converters in VGA input path. The data and I/O direction of GPIO[7:0] pins

are controlled by Reg. F4h and F5h respectively, and each bit in the register is mapped to GPIO[7:0]

correspondingly. The following description is the process to control GPIO[0] and GPIO[6] in detail, and the

control processes of GPIO[4:1] and GPIO[7] also follows in the same manner.

¨ Bi-directional GPIO control process

q Setting Reg. F5h/D0 = 0 or 1 to assign GPIO[0] as output or input.

q Writing data to Reg. F4h/D0 when GPIO[0] is assigned to output status, otherwise reading data from

Reg. F4h/D0 when GPIO[0] is input.

¨ Output only GPIO control process

q Setting Reg. F5h/D6 = 0 or 1 to assign GPIO[6] as output or tri-state.

q Setting Reg. F6h/D0 = 0 to select output source from Reg. F4h/D6 or setting it as 1 to make GPIO[6]

pin to output ADHS which is HSYNC signal decoded from VGA input Composite signal by the

MTL003.

q Writing data to F4h/D6 when GPIO[6] is assigned to output only GPIO pin, that is, F6h/D0 = 0 and

F5h/D6 = 0. If F6h/D0 is set to 1, the GPIO[6] pin outputs ADHS for AD converters in VGA input path.

3.5.6 Update Register Contents

I/O write operation to some consecutive register set can have the “Double Buffer” effect by setting the

Reg. C1h/D4. Written data is first stored in an intermediate bank of latches and then transferred to the active

register set by setting Reg. C1h/D1-0.

Revision 0.95

- 20 -

2000/06/14

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