MTL003 Просмотр технического описания (PDF) - Myson Century Inc

Номер в каталоге

Компоненты Описание

производитель

MTL003

SXGA Flat Panel Controller

Myson Century Inc 

MYSON

TECHNOLOGY

MTL003

(Rev. 0.95)

¨ Random Read

The operation of Random Read allows access to any address. Before the reading data operation, it must

issue a “dummy write” operation — the master issues the start condition, slave address and then the word

address it is to read. After the word address acknowledge, the master generating a start condition again and

slave address with R/W bit is set to 1. MTL003 then transmits the 8 bits of data. Upon the completion of

receiving data, the master will generate a stop condition instead of an Acknowledge. Ref. Fig 3.5.5.

S

T

A

R

SLAVE

T ADDRESS

WORD

ADDRESS

S

T

A

R

SLAVE

T ADDRESS

S

T

DATA

O

P

SDA

WA

A

RA

C

C

C

K

K

K

Fig. 3.5.5 Random Read

¨ Sequential Read

The initial step can be as either Current Address Read or Random Read. The first read data is transmitted in

the same manner as other read methods. However, the master generates an Acknowledge indicating that it

requires more data to read. MTL003 continues to output data for each Acknowledge received. The output

data is sequential and the internal address counter increments by one for next read data. Ref. Fig. 3.5.6.

S

T

A

R SLAVE

T ADDRESS

SDA

RA

C

K

DATA n

DATA n+1

A

A

C

C

K

K

S

T

DATA n+x

O

P

Fig. 3.5.6 Sequential Read

3.5.2 8-bit Direct Bus

The Direct Bus use AD[7:0], HWR#, HRD#, ALE, HCS# as the interface with host. ALE is used to latch read

or write address from AD[7:0] and HRD#, HWR# to access data. Ref. Fig. 3.5.7.

AD[7:0]

HRD#

HWR#

ALE

HCS#

Address and data multiplex bus.

CPU read data strobe, Active Low.

CPU write data strobe, Active Low.

ALE =1 latch read or write address, ALE=0 represents I/O data.

Enable signal for CPU access, Active Low.

Revision 0.95

- 19 -

2000/06/14

Share Link: