STPCC03 Просмотр технического описания (PDF) - STMicroelectronics
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STPCC03 Datasheet PDF : 51 Pages
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PIN DESCRIPTION
Table 2.2. Definition of Signal Pins
Signal Name
Dir
Description
Qty
BASIC CLOCKS AND RESETS
SYSRSTI#
I System Power Good Input
1
SYSRSTO#
O System Reset Output
1
XTALI
I 14.3MHz Crystal Input
1
XTALO
I/O 14.3MHz Crystal Output - External Oscillator Input
1
HCLK
I/O Host Clock (Test)
1
DEV_CLK
O 24MHz Peripheral Clock (floppy drive)
1
DCLK
I/O 27-135MHz Graphics Dot Clock
1
MEMORY INTERFACE
MCLKI
I Memory Clock Input
1
MCLKO
O Memory Clock Output
1
CS#[3:0]
O DIMM Chip Select
4
MA[11:0]
O Memory Row & Column Address
12
MD[63:0]
I/O Memory Data
64
RAS#[1:0]
O Row Address Strobe
2
CAS#[1:0]
O Column Address Strobe
2
MWE#
O Write Enable
1
DQM[7:0]
O Data Input/Output Mask
8
PCI INTERFACE
PCI_CLKI
I 33MHz PCI Input Clock
1
PCI_CLKO
O 33MHz PCI Output Clock (from internal PLL)
1
AD[31:0]
I/O PCI Address / Data
32
CBE#[3:0]
I/O Bus Commands / Byte Enables
4
FRAME#
I/O Cycle Frame
1
IRDY#
I/O Initiator Ready
1
TRDY#
I/O Target Ready
1
LOCK#
I PCI Lock
1
DEVSEL#
I/O Device Select
1
STOP#
I/O Stop Transaction
1
PAR
I/O Parity Signal Transactions
1
SERR#
O System Error
1
PCIREQ#[2:0]
I PCI Request
3
PCI_GNT#[2:0]
O PCI Grant
3
PCI_INT[3:0]
I PCI Interrupt Request
4
VDD5
I 5V Power Supply for PCI ESD protection
4
ISA CONTROL
ISA_CLK
ISA_CLK2X
OSC14M
LA[23:17]
SA[19:0]
SD[15:0]
ALE
MEMR#, MEMW#
SMEMR#, SMEMW#
O ISA Clock Output - Multiplexer Select Line For IPC
1
O ISA Clock x2 Output - Multiplexer Select Line For IPC
1
O ISA bus synchronisation clock
1
O Unlatched Address
7
I/O Latched Address
20
I/O Data Bus
16
O Address Latch Enable
1
I/O Memory Read and Memory Write
2
O System Memory Read and Memory Write
2
11/51
Release B
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
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