STPCC03 Просмотр технического описания (PDF) - STMicroelectronics

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STPCC03

PC Compatible Embeded Microprocessor

STMicroelectronics 

PIN DESCRIPTION

2.2.9 VIDEO INTERFACE

VCLK Pixel Clock Input.This signal is used to syn-

chronise data being transfered from an external

video device to either the frame buffer, or alterna-

tively out the TV output in bypass mode. This pin

can be sourced from STPC if no external VCLK is

detected, or can be input from an external video

clock source.

VIN[7:0] YUV Video Data Input CCIR 601 or 656.

Time multiplexed 4:2:2 luminance and chromi-

nance data as defined in ITU-R Rec601-2 and

Rec656 (except for TTL input levels). This bus

typically carries a stream of Cb,Y,Cr,Y digital vid-

eo at VCLK frequency, clocked on the rising edge

(by default) of VCLK.

VCS Line synchronisation Output. This pin is an

input in ODDEV+HSYNC or VSYNC + HSYNC or

VSYNC slave modes and an output in all other

modes (master/slave)

ODD_EVEN Frame Synchronisation Ourput. This

pin supports the Frame synchronisation signal. It

is an input in slave modes, except when sync is

extracted from YCrCbdata, and an output in mas-

ter mode and when sync is extracted from YCrCb

data

The signal is synchronous to rising edge of DCLK.

The default polarity for this pin is:

- odd (not-top) field : LOW level

- even (bottom) field : HIGH level

2.2.10 TV OUTPUT

RED_TV / C_TV Analog video outputs synchro-

nized with CVBS. This output is current-driven and

must be connected to analog ground over a load

resistor (RLOAD). Following the load resistor, a

simple analog low pass filter is recommended. In

S-VHS mode, this is the Chrominance Output.

GREEN_TV / Y_TV Analog video outputs syn-

chronized with CVBS. This output is current-driv-

en and must be connected to analog ground over

a load resistor (RLOAD). Following the load resis-

tor, a simple analog low pass filter is recommend-

ed. In S-VHS mode, this is the Luminance Output.

BLUE_TV / CVBS Analog video outputs synchro-

nized with CVBS. This output is current-driven and

must be connected to analog ground over a load

resistor (RLOAD). Following the load resistor, a

simple analog low pass filter is recommended. In

S-VHS mode, this is a second composite output.

CVBS Analog video composite output (luminance/

chrominance). CVBS is current-driven and must

be connected to analog ground over a load resis-

tor (RLOAD). Following the load resistor, a simple

analog low pass filter is recommended.

IREF1_TV Ref. current for CVBS 10-bit DAC.

IREF2_TV Reference current for RGB 9-bit DAC.

VREF1_TV Ref. voltage for CVBS 10-bit DAC.

VREF2_TV Reference voltage for RGB 9-bit DAC.

VSSA_TV Analog VSS for DACs.

VDDA_TV Analog VDD for DACs.

19/51

Release B

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

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