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STLC5445

QUAD LINE FEED CONTROLLER

STMicroelectronics 

STLC5445

The status detector bits reading if a read operation is performed.

A0 must be valid on the falling edge of the signal applied at the ALE (Address Latch Enable) pin or during the

read and write operations if ALE is tied High.

NOTE: A delay of at least 1ms is required between a LER writing and the next LER reading. Subsequent LER

reading operations do not have this constraint.

The line output drivers' switch on or switch off requests are implemented by first selecting the LER register and

then by writing in its D0-D3 bits a 1 (turn on request) or a 0 (turn off request). D0 controls channel 0, D1 channel

1 and so on. If the requests are accepted by the Thermal monitoring block and (if activated) by the Power on

sequencer, the bits stored in the LER register are copied in the LEC register whose status (1 = turn on; 0 = turn

off) directly controls the output drivers' ON/OFF condition.

For each of the four channels, in MPI mode the following six status detector bits are available:

The COD, OLD and TOR bits whose function has already been described at the beginning of the Logic

Section paragraph.

The LER and the LEC bits.

The POF (Power On Sequencer) bit already described at the Power on sequencer paragraph.

The status detector bits reading is performed by first writing in the 2 - 0 bits of the IAR register (via the D2-D0

bus lines) a three bits code used to select which of the six available status detector bits type has to be red. A0

must then to be set at 1 and the reading cycle has to be performed. The status detector bits' selection codes

are listed in the following table.

If (for example) a 010 code has been written in the IAR, the output on the D0 - D3 lines at the end of the reading

cycle will be the COD0 - COD3 bits.

Please, note that since the red data are not latched (apart from the TOR status detector bits of the channels

whose output drivers are switched on), the user should filter them (multiple samples) to ensure theirs integrity.

IAR2

IAR1

IAR0

Selected status detector bits type

0

0

0

POF

0

0

1

OLD

0

1

0

COD

0

1

1

LEC

1

0

0

RESERVED

1

0

1

RESERVED

1

1

0

LER

1

1

1

TOR

As already explained the IAR is a four bits register but only three bits (D2 - D0) are required to select one of the

six available status detector bits types. The fourth IAR bit (D3) is the I bit and is used to enable (1) or disable

(0) the generation of the interrupt signal INTN that, via the INTN pin, can alerts an external microprocessor when

a current overload condition occurs. INTN is active (Low level) when at least one of the CODn status detector

bits is active (High level). When the four CODn status detector bits are Low, INTN goes inactive (High): this

clearly means that INTN will also go inactive if (due to thermal overload) the QLFC automatically disables the

output driver of the channel that caused the interrupt or if the external microprocessor disables that line via the

LER register.

The interrupt function can also be disabled (INTN remains permanently High) by applying a Low level on the

RESETN pin.

As previously explained, when a reading operation is performed while A0 = 0 the four bits actually written in the IAR

register can be read on the D3 - D0 bus lines. We already know that the D2 - D0 bits represent the status detector bits

selection code. The D3 bit is the T bit: it is High only when the internal chip's temperature exceeds 160°C.

20/23

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