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STLC5445

QUAD LINE FEED CONTROLLER

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STLC5445

latched and is active (Low level) when at least one of the CODn status detector bits is active

(High level). When the four CODn status detector bits are Low, INTN goes inactive (High). INTN

will also go inactive if (due to thermal overload) the QLFC automatically disables the output driv-

er of the channel that caused the interrupt, or if the external microprocessor disables that line

via the Line Enable Register (LER). The interrupt function can be disabled (INTN remains per-

manently High) via the Indirect Address Register (IAR) or a Low level on the RESETN pin.

NACKn (n=0-3)Logic I/O.

These pins have double names (see the block diagram at page 3) because they perform a dou-

ble function: one in Parallel mode ( PSC = 0 ), and another in MPI mode ( PSC = 1).

In Parallel mode each NACKn acts as an open drain output and gives the channel's status in-

formation.

The NACKn bit goes in high impedance state (bit = 1 if a NACKn pull up is provided) when at

least one of these conditions is verified:

The current on the relative line reaches the current limit programmed by the user.

The chip's temperature reach the thermal alarm threshold.

The line driver is in the Power on phase.

When the ESn input is set Low, the corresponding NACKn is set to zero.

In MPI mode the four pins become D3 - D0 and act as a bidirectional data bus with three state

capability. The four bidirectional data bus lines are used to exchange information with an exter-

nal microprocessor. D0 is the least significant bit and D3 is the most significant bit. An High Lev-

el on the data bus corresponds to a logical 1. When the chip select bit (CSN) is Low, these lines

act as inputs when WRN is Low and as outputs when RDN is Low. When CSN is High the D3

- D0 pins are in a high impedance state.

PSC

Logic input.

This pin is used to select one of the two available logic interfaces.

PSC = 0: Parallel mode.

PSC = 1: MPI mode.

ERLn (n=0A-3B) Logic inputs.

Each ERLn pin controls directly the respective relay driver's DMOS:

ERLn = 0 : Switch off the relay driver.

ERLn = 1 : Switch on the relay driver.

RLn (n=0A-3B) Relay drivers' output.

Each of the eight RLn pins is connected to the drain of an internal DMOS switch (see the block

diagram at page 3) which acts as a driver for an external relay to be supplied from VCC. The

relay drivers' current flows to ground through the RGND pins. Each output can sink up to 70

mA. An internal clamping circuit is provided, so no external kickback diodes are required.

CODCn

(n=0-3)

When a line over current condition exists, the output driver of the overloaded channel instanta-

neously limits the line current at the value programmed by means of the external RLIM resistor.

In this condition the Current Overload Detector bit (COD) switches to a High logic level.

When operating in MPI mode this bit can, for each of the four channels, be red by the external

microprocessor in order to check which channel (if any) is overloaded.

When in parallel mode each COD bit is internally OR combined with two other bits in order to

generate the NACKn bit.

Since in the ISDN application it can happens that the sum of the DC line current and the super-

imposed signal peaks, easily exceeds the needed DC current limit, the COD generation circuitry

has been arranged in such a way that the COD bit will be pushed High only if the current over-

load persists for at least 20ms: this eliminates any spurious High level COD / NACK. The men-

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