CXG1030N Просмотр технического описания (PDF) - Sony Semiconductor
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производитель
CXG1030N Datasheet PDF : 5 Pages
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Block Diagram
VDD1 VDD2 VDD3
RFIN
RFOUT
VGG1
VCTL VGG2
Gate Bias Circuit
Pin Configuration
1
GND
RFIN
GND
VDD1
GND
VDD2
GND
VDD3
Gate adjustment pin
1kΩ
VGG2
VGG1
CXG1030N
16
GND
VGG1
VCTL
GND
VGG2
GND
RFOUT
GND
Recommended Current Adjustment Method
(1) VGG2/PIN separate adjustment
(VGG2 adjustment 1)
(PIN adjustment 1)
When the RF input
(PIN) is off, the current
consumption (IDD) is
adjusted to 170 mA.
The output power
(POUT) is adjusted
to 21.0 dBm.
Variation of IDD and
POUT due to adjustment
IDD=170±20 mA
POUT=21.0 dBm
(VGG2 adjustment 2)
The current
consumption (IDD)
is finely adjusted to
170 mA.
IDD=170 mA
POUT=21.0±0.2 dBm
(PIN adjustment 2)
The output power
(POUT) is finely
adjusted to 21.0 dBm.
IDD=170±5 mA
POUT=21.0 dBm
(2) Simple adjustment
(IDD read)
When the RF input (PIN)
is off, the gate voltage
(VGG2) is set to 0.4 V
and IDD is read.
Variation of IDD and POUT
due to adjustment
(VGG2 setting)
The formula∗1 where
VGG2=f (IDD: VGG2=0.4 V)
is used to set VGG2.
∗1 e.g. VGG2=a-b × IDD
(PIN adjustment)
The output power (POUT)
is adjusted to 21.0 dBm.
IDD=170±5 mA
POUT=21.0 dBm
—2—
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