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OR3TP12

ORCA® OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

Agere -> LSI Corporation 

Data Sheet

March 2000

ORCA OR3TP12 FPSC

Embedded Master/Target PCI Interface

Description (continued)

PLC Logic

Each PFU within a PLC contains eight 4-input (16-bit)

LUTs, eight latches/flip-flops (FFs), and one additional

flip-flop that may be used independently or with arith-

metic functions.

The PFU is organized in a twin-quad fashion: two sets

of four LUTs and FFs that can be controlled indepen-

dently. LUTs may also be combined for use in arith-

metic functions using fast-carry chain logic in either

4-bit or 8-bit modes. The carry-out of either mode may

be registered in the ninth FF for pipelining. Each PFU

may also be configured as a synchronous 32 × 4

single- or dual-port RAM or ROM. The FFs (or latches)

may obtain input from LUT outputs or directly from

invertible PFU inputs, or they can be tied high or tied

low. The FFs also have programmable clock polarity,

clock enables, and local set/reset.

The SLIC is connected to PLC routing resources and to

the outputs of the PFU. It contains 3-state, bidirectional

buffers and logic to perform up to a 10-bit AND function

for decoding, or an AND-OR with optional INVERT AOI

to perform PAL-like functions. The 3-state drivers in the

SLIC and their direct connections to the PFU outputs

make fast, true 3-state buses possible within the FPGA

logic, reducing required routing and allowing for real-

world system performance.

PIC Logic

The Series 3T PIC addresses the demand for ever-

increasing system clock speeds. Each PIC contains

four programmable inputs/outputs (PIOs) and routing

resources. On the input side, each PIO contains a fast-

capture latch that is clocked by an ExpressCLK. This

latch is followed by a latch/FF that is clocked by a sys-

tem clock from the internal general clock routing. The

combination provides for very low setup requirements

and zero-hold times for signals coming on-chip. It may

also be used to demultiplex an input signal, such as a

multiplexed address/data signal, and register the sig-

nals without explicitly building a demultiplexer. Two

input signals are available to the PLC array from each

PIO, and the ORCA Series 2 capability to use any input

pin as a clock or other global input is maintained.

On the output side of each PIO, two outputs from the

PLC array can be routed to each output flip-flop, and

logic can be associated with each I/O pad. The output

logic associated with each pad allows for multiplexing

of output signals and other functions of two output sig-

nals.

The output FF, in combination with output signal multi-

plexing, is particularly useful for registering address

signals to be multiplexed with data, allowing a full clock

cycle for the data to propagate to the output. The I/O

buffer associated with each pad is the same as the

ORCA Series 3T buffer.

System Features

The Series 3 also provides system-level functionality

by means of its dual-use microprocessor interface

(MPI) and its innovative PCM. These functional blocks

allow for easy glueless system interfacing and the

capability to adjust to varying conditions in today’s

high-speed systems. Since these and all other Series

3T features are available in every Series 3+ FPSC,

they can also interface to the embedded core providing

for easier system integration.

Lucent Technologies Inc.

9

Lucent Technologies Inc.

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