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OR3TP12

ORCA® OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

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ORCA OR3TP12 FPSC

Embedded Master/Target PCI Interface

Data Sheet

March 2000

Description (continued)

FPSC Design Kit

Development is facilitated by an FPSC Design Kit

which, together with ORCA Foundry and third-party

synthesis and simulation engines, provides all software

and documentation required to design and verify an

FPSC implementation. Included in the kit are the FPSC

configuration manager, Verilog * and VHDL* simulation

models, all necessary synthesis libraries, and complete

online documentation. The kit's software couples with

ORCA Foundry under the control of the ORCA Foundry

Control Center (OFCC), providing a seamless FPSC

design environment. More information can be obtained

by visiting the ORCA website or contacting a local

sales office, both listed on the last page of this docu-

ment.

ORCA Foundry Development System

The ORCA Foundry Development System is used to

process a design from a netlist to a configured FPSC.

This system is used to map a design onto the ORCA

architecture and then place and route it using ORCA

Foundry’s timing-driven tools. The development system

also includes interfaces to, and libraries for, other popu-

lar CAE tools for design entry, synthesis, simulation,

and timing analysis.

The ORCA Foundry Development System interfaces to

front-end design entry tools and provides the tools to

produce a configured FPSC. In the design flow, the

user defines the functionality of the FPGA portion of

the FPSC and embedded core settings at design entry

stage. The embedded core options determine the

FPSC functionality.

Following design entry, the development system’s map,

place, and route tools translate the netlist into a routed

FPSC. A static timing analysis tool is provided to deter-

mine design speed, and a back-annotated netlist can

be created to allow simulation. Simulation output files

from ORCA Foundry are also compatible with many

third-party analysis tools. Its bit stream generator is

then used to generate the configuration data which is

loaded into the FPSC’s internal configuration RAM.

When using the FPSC configuration manager, the user

selects options that affect the functionality of the FPSC.

Combined with the front-end tools, ORCA Foundry pro-

duces configuration data that implements the various

logic and routing options discussed in this data sheet.

FPGA Logic Overview

ORCA Series 3 FPGA logic is a new generation of

SRAM-based FPGA logic built on the successful

Series 2 FPGA line from Lucent Technologies Micro-

electronics Group, with enhancements and innovations

geared toward today’s high-speed designs and tomor-

row’s systems on a single chip. Designed from the start

to be synthesis friendly and to reduce place and route

times while maintaining the complete routability of the

ORCA Series 2 devices, the Series 3 more than dou-

bles the logic available in each logic block and incorpo-

rates system-level features that can further reduce

logic requirements and increase system speed. ORCA

Series 3 devices contain many new patented enhance-

ments and are offered in a variety of packages, speed

grades, and temperature ranges.

ORCA Series 3 FPGA logic consists of three basic ele-

ments: PLCs, programmable input/output cells (PICs),

and system-level features. An array of PLCs is sur-

rounded by PICs. Each PLC contains a PFU, a SLIC,

local routing resources, and configuration RAM. Most

of the FPGA logic is performed in the PFU, but decod-

ers, PAL-like functions, and 3-state buffering can be

performed in the SLIC. The PICs provide device inputs

and outputs and can be used to register signals and to

perform input demultiplexing, output multiplexing, and

other functions on two output signals. Some of the sys-

tem-level functions include the new microprocessor

interface (MPI) and the PCM.

* Verilog and VHDL are registered trademarks of Cadance Design

Systems, Inc.

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