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OR3TP12

ORCA® OR3TP12 Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

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ORCA OR3TP12 FPSC

Embedded Master/Target PCI Interface

Data Sheet

March 2000

Description (continued)

Routing

The abundant routing resources of ORCA Series 3

FPGA logic are organized to route signals individually

or as buses with related control signals. Clocks are

routed on a low-skew, high-speed distribution network

and may be sourced from PLC logic, externally from

any I/O pad, or from the very fast ExpressCLK pins.

ExpressCLKs may be glitchlessly and independently

enabled and disabled with a programmable control sig-

nal using the new StopCLK feature. The improved PIC

routing resources are now similar to the patented intra-

PLC routing resources and provide great flexibility in

moving signals to and from the PIOs. This flexibility

translates into an improved capability to route designs

at the required speeds when the I/O signals have been

locked to specific pins.

Configuration

The FPGA logic’s functionality is determined by internal

configuration RAM. The FPGA logic’s internal initializa-

tion/configuration circuitry loads the configuration data

at powerup or under system control. The RAM is

loaded by using one of several configuration sources,

including serial EEPROM, the microprocessor inter-

face, or the embedded function core.

More Series 3 Information

For more information on Series 3 FPGAs, please refer

to the Series 3 FPGA data sheet, available on the

ORCA worldwide website or by contacting Lucent

Technologies as directed on the back of this data

sheet.

OR3TP12 Overview

Device Layout

The OR3TP12 FPSC provides a PCI local bus core

(with FIFOs) combined with FPGA logic. The device is

based on a 3.3 V OR3T55 FPGA. The OR3T55 has an

18 × 18 array of PLCs. For the OR3TP12, the bottom

four rows of PLCs in the array were replaced with the

embedded PCI bus core. Figure 1 shows a schematic

view of the OR3TP12. The upper portion of the device

is a 14 × 18 array of PLCs surrounded on the left, top,

and right by programmable input/output cells (PICs). At

the bottom of the PLC array are interface cells connect-

ing to the embedded core region. The embedded core

region contains the PCI bus functionality of the device.

It is surrounded on the left, bottom, and right by PCI

bus dedicated I/Os as well as power and special func-

tion FPGA pins. Also shown are the interquad routing

blocks (hIQ, vIQ) present in the Series 3T FPGA

devices. System-level functions (located in the corners

of the PLC array), routing resources, and configuration

RAM are not shown in Figure 1.

OR3TP12 PCI Bus Core Overview

The OR3TP12 embedded core comprises a PCI bus

interface with independent Master and Target control-

lers, FIFO memories, control logic for data buffering, a

dual-/quad-port interface to the FPGA logic which per-

forms data packing and multiplexing, and logic to sup-

port the embedded core and FPGA configuration. A

detailed description of all of the features and functional-

ity of the OR3TP12 embedded core is provided in the

following sections.

PCI Bus Interface

The OR3TP12 PCI bus core is compliant to Revision

2.1 of the PCI Local Bus specification. It is capable of

no-wait-state, full-burst operation at all of the rate/data

width combinations described in Table 1 as well as at a

50 MHz specification that provides a speed increase

over the 33 MHz specification and a larger bus loading

capability than the 66 MHz specification. The

OR3TP12 operates in either the 3.3 V or 5 V PCI sig-

naling environment and is automatically configured for

the appropriate environment by a PCI bus vio pin.

Independent Master and Target controllers are pro-

vided for use in systems requiring Master/Target or Tar-

get only operation. Six 32-bit base address registers

(BARs) are provided for decoding the address space of

the PCI device, and these six 32-bit registers can be

combined in pairs to produce 64-bit BARs. Dual-

address cycles are supported when the PCI bus is

either 32 or 64 bits wide. The BARs work in either the

I/O or the memory space of the device and can be con-

figured as prefetchable or nonprefetchable.

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