DAC8413BTC/883 Просмотр технического описания (PDF) - Analog Devices

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DAC8413BTC/883

Quad, 12-Bit DAC Voltage Output with Readback

Analog Devices 

DAC8412/DAC8413

10.0

1.00

0.10

VDD = +15V

VSS = –15V

VREFH = +10V

VREFL = –10V

TA = +25؇C

0.01

0.001

1

10

100

1000

NOISE FREQUENCY – Hz

10000

Figure 29. DAC8412 Noise

Frequency vs. Noise Density

0

30

VDD = +15V

VSS = –15V

20

VREFH = +10V

VREFL = –10V

10

TA = +25؇C

DATA = 000H

0

+ISC

–10

–20

–ISC

–30

0

–25 –20 –15 –10 –5 0 5 10 15 20 25

VOUT – Volts

Figure 30. IOUT vs. VOUT

1

20uV/DIV

CH1 MEAN

66.19␮V

VDD = +15V

VSS = –15V

VREFH = +10V

VREFL = –10V

TA = +25؇C

M 200␮s A CH1 12.9mV

Figure 31. Broadband Noise

25

20

VDD = +15V

VSS = 0V

15 VREFH = +10V

VREFL = 0V

10 TA = +25؇C

5 DATA = 800H

+ISC

0

–5

–10

–15

–ISC

–20

–25

–6 –4 –2

0

2

4

6

VOUT – Volts

Figure 32. IOUT vs. VOUT

10␮s

1V

4␮s

GLITCH AT DAC OUTPUT

2

1

DEGLITCHER OUTPUT

1V

CH2 1.86V

Figure 33. Glitch and Deglitched Results

OPERATION

Introduction

The DAC8412 and DAC8413 are quad, voltage output, 12-bit

parallel input DACs featuring a 12-bit data bus with readback

capability. The only differences between the DAC8412 and

DAC8413 are the reset functions. The DAC8412 resets to mid-

scale (code 800H) and the DAC8413 resets to minimum scale

(code 000H).

The ability to operate from a single +5 V supply is a unique fea-

ture of these DACs.

Operation of the DAC8412 and DAC8413 can be viewed by

dividing the system into three separate functional groups: the

digital I/O and logic, the digital to analog converters and the output

amplifiers.

DACs

Each DAC is a voltage switched, high impedance (R = 50 kΩ),

R-2R ladder configuration. Each 2R resistor is driven by a pair of

switches that connect the resistor to either VREFH or VREFL.

Glitch

Worst-case glitch occurs at the transition between half-scale

digital code 1000 0000 0000 to half-scale minus 1 LSB, 0111

1111 1111. It can be measured at about 2 V µs. (See Figure 33.)

For demanding applications such as waveform generation or

precision instrumentation control, a deglitcher circuit can be

implemented with a standard sample-and-hold circuit. (See

Figure 34.) When CS is enabled by synchronizing the hold

period to be longer than the glitch tradition, the output voltage

can be smoothed with minimum disturbance. A quad sample-

and-hold amplifier, SMP04, has been used to illustrate the

deglitching result. (See Figure 33.)

DACOUT

S/H

DACOUT'

DACOUT

CS

S/H

DACOUT'

H

S

H

S

Figure 34. Deglitcher Circuit

–10–

REV. D

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