MT8986AE Просмотр технического описания (PDF) - Mitel Networks

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MT8986AE

CMOS ST-BUS™ FAMILY Multiple Rate Digital Switch

Mitel Networks 

MT8986

Register (FIO). If this function is not required in the

user's applications, the FIO register should be set up

during system initialization to a state where offset

functions are disabled.

Delay Through the MT8986

The switching of information from the input serial

streams to the output serial streams results in a

delay. Depending on the type of information to be

switched, the MT8986 device can be programmed to

perform time-slot interchange functions with different

throughput delay capabilities on a per-channel basis.

For voice applications, variable throughput delay can

be selected ensuring minimum delay between input

and output data. In wideband data applications,

constant throughput delay can be selected

maintaining the frame integrity of the information

through the switch.

The delay through the MT8986 device varies

according to the type of throughput delay selected in

the V/C bit of the connect memory high.

Variable Throughput Delay Mode (V/C bit = 0)

it is independent of the input and output streams.

The minimum delay achievable in the MT8986

depends on the data rate selected for the serial

streams. For instance, for 2.048 Mb/s the minimum

delay achieved corresponds to three time-slots. For

4.096 Mb/s it corresponds to five time-slots while for

8.192 Mb/s it is nine time-slots. Switching

configurations with input and output channels that

provides more than its corresponding minimum

throughput delay, will have a throughput delay equal

to the difference between the output and input

channels; i.e., the throughput delay will be less than

one frame period. Table 3a shows the MT8986

throughput delay for each data rate operation.

Different I/O Data Rates

Except for 2 Mb/s to 4 Mb/s and 2 Mb/s to 8 Mb/s

rate conversion operations, the throughput delay in

the MT8986 may vary according to the output stream

used for switching.

Table 3b explains the worst case conditions for the

throughput delay when different I/O data rate

switching configurations are used.

Identical I/O Data Rates

Constant Throughput Delay mode (V/C bit = 1)

The delay in this mode is dependent on the

combination of source and destination channels and

In this mode frame sequence integrity is maintained

in both Identical and Different I/O Data Rate

Input Rate

m<n

Output Channel (# m)

m=n, n+1, n+2

m= n+3, n+4

m=n+5, .. n+8

m > n+8

2.048 Mb/s

4.096 Mb/s

32-(n-m) t.s.

64-(n-m) t.s.

m-n + 32 t.s.

m-n + 64 t.s.

m-n t.s.

m-n+64 t.s.

m-n t.s.

m-n t.s.

m-n t.s.

m-n t.s.

8.192 Mb/s 128-(n-m) t.s. m-n + 128 t.s. m-n+128 t.s.

m-n+128 t.s.

m-n t.s.

Table 3a. Variable Throughput Delay Values for Identical I/O Rate Applications

n= input channel, t.s. = time-slot

I/O Data Rate

Configuration

0, 1

Output Stream Used

2, 3

4, 5

6, 7

2 Mb/s to 4 Mb/s dmin=5x 4Mb/s t.s.

dmax=1 fr.+(4x 4Mb/s t.s.)

2 Mb/s to 8 Mb/s dmin=9x 8Mb/s t.s.

dmax=1 fr.+(8x 8Mb/s t.s.)

4 Mb/s to 2 Mb/s dmin=3x 2Mb/s t.s.

dmax=1 fr.+(2x 2Mb/s t.s.)

dmin=(2x 2Mb/s t.s.)+(1x 4Mb/s t.s.)

dmax=1 fr.+(1x 2Mb/s t.s.)+(1x 4Mb/s t.s.)

8 Mb/s to 2 Mb/s

dmin=3x 2Mb/s t.s.

dmax=1 fr.+(2x 2Mb/s

t.s.)

dmin=(2x 2Mb/s t.s.)+

(3x 8Mb/s t.s.)

dmax=1 fr.+(1x 2Mb/s

t.s.)+(3x 8Mb/s t.s.)

dmin=(2x 2Mb/s t.s.)+

(2x 8Mb/s t.s.)

dmax=1 fr.+(1x 2Mb/s

t.s.)+(2x 8Mb/s t.s.)

dmin=(2x 2Mb/s t.s.)+

(1x 8Mb/s t.s.)

dmax=1 fr.+(1x 2Mb/s

t.s.)+(1x 8Mb/s t.s.)

Table 3b. Min/Max Throughput Delay Values for Different I/O Rate Applications

Notes: dmin and dmax are measured in time-slots and at the point in time when the output channel is completely shifted out.

t.s. = time-slot

fr. = 125 µs frame

2 Mb/s t.s. = 3.9 µs

4 Mb/s t.s. = 1.95 µs

8 Mb/s t.s. = 0.975 µs

2-71

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