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FAN5240 Просмотр технического описания (PDF) - Fairchild Semiconductor

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FAN5240 Datasheet PDF : 19 Pages
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Current Processing Section
The following discussion refers to Figure 6.
Setting RSENSE
Each phase current is sampled about 200nS after the
SW node crosses 0V. For proper converter operation,
choose an RSENSE value of:
RSENSE
=
R-----D----S---(--O----N----)-------I--M----A----X-
40µA
With Active Droop, the output voltage varies with the load
as if a resistor were connected in series with the con-
verter’s output, in other words, it's effect is to raise the
output resistance of the converter.
1.2
VDROOP
which is about 1K for the components in Figure 1.
Active Droop
The core converter incorporates a proprietary output
voltage droop method for optimum handling of fast load
transients found in modern processors.
“Active droop” or voltage positioning is now widely used
in the computer power applications. The technique is
based on raising the converter voltage at light load in
anticipation of a step increase in load current, and con-
versely, lowering VCORE in anticipation of a step
decrease in load current.
ILOAD
IMAX
Figure 5. Active Droop
To get the most from the Active Droop, its magnitude
should be scaled to match the output capacitor’s ESR
voltage drop.
VDROOP = IMAX × ESR
(6)
Active Droop allows the size and cost of the output
capacitors required to handle CPU current transients to
be reduced. The reduction may be almost a factor of 2
when compared to a system without Active Droop.
ISNS1-ISNS2
ISNS2
B-A
A ΣB
ISNS2-ISNS1
A-B
ISNS2
5
To A1 (+)
S/H
ISNS1
ISNS1
5
V to I
in +
ISNS1
8 in D
0.9V
ISNS1 RSENSE
LDRV1
PGND1
ILIM RILIM
ILIM det. 1
2.5V
I2 =
ILIM
ILIM mirror
Figure 6. Current Limit and Active Droop Circuits
10
www.fairchildsemi.com
FAN5240 Rev. 1.2.0

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