68901N04 Просмотр технического описания (PDF) - STMicroelectronics

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68901N04

MULTI–FUNCTION PERIPHERAL

STMicroelectronics 

MK68901

Figure 12 : Timer A and B Control Registers.

* Unused bits : read as zeros.

In the delay mode, the prescaler is always active.

A count pulse will be applied to the main timer unit

each time the prescribed number of timer clock cy-

cles has elapsed. Thus, if the prescaler is program-

med to divide by ten, a count pulse will be applied

to the main counter every ten cycles of the timer

clock.

Each time a count pulse is applied to the main coun-

ter, it will decrement its contents. The main counter

is initially loaded by writing to the Timer Data Regis-

ter. Each count pulse will cause the current count to

decrement. When the timer has decremented down

to ”01” , the next count pulse will not cause it to de-

crement to ”00”. Instead, the next count pulse will

cause the timer to be reloaded from the Timer Data

Register. Additionally, a ”Time out” pulse will be pro-

duced. This Time Out pulse is coupled to the timer

interrupt channel, and, if that channel is enabled, an

interrupt will be produced. The Time Out pulse is al-

so coupled to the timer output pin and will cause the

pin to change states. The output will remain in this

new state until the next Time Out pulse occurs. Thus

the output will complete one full cycle for each two

Time Out pulses.

If, for example, the prescaler were programmed to

divide by ten, and the Timer Data Register were loa-

V000359

ded with 100 (decimal), the main counter would de-

crement once for every ten cycles of the timer clock.

A Time Out pulse will occur (hence an interrupt if that

channel is enabled) every 1000 cycles of the timer

clock, and the timer output will complete one full cy-

cle every 2000 cycles of the timer clock.

The main counter is an 8-bit binary down counter. It

may be read at any time by reading the Timer Data

Register. The information read is the information

last clocked into the timer read register when the DS

pin had last gone high prior to the current read cycle.

When written, data is loaded into the Timer Data Re-

gister, and the main counter, if the timer is stopped.

If the Timer Data Register is written while the timer

is running, the new word is not loaded into the timer

until it counts through H”01”. However, if the timer

is written while it is counting through H”01”, an inde-

terminate value will be written into the timer constant

register. This may be circumvented by ensuring that

the data register is not written when the count is

H”01”.

If the main counter is loaded with ”01”, a Time Out

Pulse will occur every time the prescaler presents

a count pulse to the main counter. If loaded with

”00”, a Time Out pulse will occur every 256 count

pulses.

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