ADP3804 Просмотр технического описания (PDF) - Analog Devices

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ADP3804

High Frequency Switch Mode Li-Ion Battery Charger

Analog Devices 

ADP3804

2.5 V Precision Reference

UVLO

The voltage at the BAT pin is compared to an internal preci-

Under-Voltage Lock-Out, UVLO, is included in the ADP3804

sion, low temperature drift reference of 2.5 V. The reference is to ensure proper start-up. As VCC rises above 1 V, the refer-

available externally at the REF pin. This pin should be by-

ence and regulators will track VCC until they reach their final

passed with a 100 pF capacitor to the analog ground pin,

voltages. However, the rest of the circuitry is held off by the

AGND. The reference can be used as a precision voltage exter- UVLO comparator. The UVLO comparator monitors both

nally. However, the current draw should not be greater than

regulators to ensure that they are above 5 V before turning on

100 µA, and no noisy, switching type loads should be con-

the main charger circuitry. This occurs when VCC reaches 6 V.

nected.

Monitoring the regulator outputs makes sure that the charger

6 V Regulator

The 6 V regulator supplies power to most of the analog cir-

cuitry on the ADP3804. This regulator should be bypassed to

circuitry and driver stage have sufficient voltage to operate

normally. The UVLO comparator includes 300 mV of hyster-

esis to prevent oscillations near the threshold.

AGND with a 10 nF capacitor. This reference has a 3 mA

Startup Sequence

source capability to power external loads if needed.

During a startup from either SD going high or VCC exceeding

CCCV

the UVLO threshold, the ADP3804 initiates a soft-start se-

An open drain output is available to signal when the ADP3804 quence. The soft-start timing is set by the compensation ca-

switches from CC to CV charging. An external pull-up resistor pacitor at the COMP pin and an internal 40 µA source.

of 100 kW to REG or other pull-up voltage is required for this

function. If the CCCV signal is not needed, the pin should be

left open. The CCCV function uses two comparators to moni-

Y tor the battery voltage and the charge current. In order for the

R CCCV pin to go high, signaling CV mode, the battery voltage

A must be higher than 95% of its final value, and the current

must be less than 80% of its programmed value. If the battery

IN voltage is less than 95% then CCCV will be low regardless of

L the actual current flowing. This is to prevent a false output

IM A during startup when the current is low.

L IC System Current Sense

E An uncommitted differential amplifier is provided for addi-

N tional high side current sensing. This amplifier, AMP2, has a

PR H fixed gain of 50 V/V from the SYS+ and SYS- pins to the ana-

C A log output at ISYS. ISYS has a 1 µA source capability to drive

E T an external load. The common mode range of the input pins is

T A from 4 V to VCC. This amplifier is the only part of the

D ADP3804 that remains active during shutdown. The power to

Initially, both DRVH and DRVL are held low until VCOMP

reaches 1 V. This delay time is set by:

t DELAY

= CCOMP - 1V

40mA

(5)

For a 1 µF COMP capacitor, tDELAY is 25 msec. After this

initial delay, DRVL is turned on first for one period to give the

boost capacitor time to charge up. The duty cycle then ramps

up to its final value with the same ramp rate given for tDELAY.

For example, if VIN is 16 V and the battery is 10 V when charg-

ing is started, the duty cycle will be approximately 65%, corre-

sponding to a VCOMP of ~2 V. The time for the duty cycle to

ramp from 0% at VCOMP = 1 V to 65% at VCOMP = 2 V is ap-

proximately 25 msec.

Loop Feed Forward

As the startup sequence discussion shows, the response time at

COMP is slowed by the large compensation capacitor. To

speed up the response, two comparators can quickly feed for-

this block is derived from the bias current on the SYS+ and

ward around the normal control loop and pull the COMP node

SYS- pins.

to ground to limit any over shoot in either short circuit or over-

A separate comparator is included to provide a flag when the

voltage conditions. The over-voltage comparator has a trip

voltage at ISYS rises above 2.5 V. The open drain output is

point set to 20% higher than the final battery voltage. The

capable of sinking 1 µA when the threshold is exceeded. This

over-current comparator threshold is set to 200 mV across the

comparator is turned off during shutdown to conserve power.

CS pins, which is 25% above the maximum programmable

Shutdown

A high impedance CMOS logic input is provided to turn off the

ADP3804. When the voltage on SD is less than 0.8 V, the

ADP3804 is placed in low power shutdown. With the exception

of the system current sense amplifier, AMP2, all other circuitry

is turned off. The reference and regulators are pulled to ground

during shutdown and all switching is stopped. During this

state, the supply current is less than 10 µA. Also, the BAT,

threshold. When these comparators are tripped, a normal soft-

start sequence is initiated. This will give 0% duty cycle with

DRVH off and DRVL on. The over-voltage comparator is

valuable when the battery is removed during charging. In this

case, the current in the inductor causes the output voltage to

spike up, and the comparator limits the maximum voltage.

Neither of these comparators affect the loop under normal

charging conditions.

CS+, CS-, and SW pins go to high impedance to minimize

current drain from the battery.

REV. PrI

–7–

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