CXD1958Q Просмотр технического описания (PDF) - Sony Semiconductor
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CXD1958Q Datasheet PDF : 48 Pages
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CXD1958Q
2-7. Decision Device
The Decision Device block performs data slicing and symbol/bit mapping for 16, 64 and 256 QAM
constellations. This block can also automatically or manually compensate for an inverted IF spectrum under
I2C bus control. Modulation scheme recognition can be preset via I2C bus for fast acquisition.
2-8. Configuration and Control
Configuration and control is handled by a register bank accessible to an external processor over an I2C serial
bus.
A pre-processor state machine controls the initial acquisition process until synchronisation is achieved. Once
the pre-processor has acquired lock to the input symbol rate the equalizer section is enabled. Once enabled,
Equalizer operation is also controlled by a state machine. Once Equalizer acquisition is achieved the condition
is then maintained based upon acquisition and mode control information, supplied from the configuration
registers, and MPEG Transport Stream status data from the FEC block.
3. Post-Processor
Post-processing on the demodulated QAM/TCM signal implements the DAVIC MMDS standard. This includes
differential decoding of the two most significant symbol bits (QAM mode only), mapping of decoded symbols
onto bytes, Forney convolutional de-interleaving of the bytes (I = 12, and I = 204) to remove burst errors,
Reed-Solomon (255, 239) error correction, MPEG-2 sync byte inversion and data stream de-randomization.
Finally a baseband interface is included that provides an MPEG-2 compliant transport stream to the device
output.
Unsliced I Q
Values from
Equalizer
Sliced
Symbols
from
Equalizer
BER
Figures
Lock
Flag
Lost Lock
Flag
TCM Decoder
Differential
Decoder
BER
Measurement
SYNC Detect & Loss
&
ISYNC Detect
FEC Register Bank
(FRB)
Inverted
SYNC Flag
m-tuple
mapper
&
SYNC
Detect
BB0
SYNC
Flag
De-
Interleaver BB1
SYNC
Flag
Reed
Solomon
Decoder
BB2
SYNC
Flag
Energy
Dispersal
Removal
BB3
SYNC
Flag
Baseband Transport
Interface Stream Data
Fig. 4. Post-Processor Block Diagram
–9–
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