CXD1958Q Просмотр технического описания (PDF) - Sony Semiconductor

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производитель

CXD1958Q

MMDS TCM/QAM Demodulator + FEC + ADC

Sony Semiconductor 

Description of Functions

CXD1958Q

VIN

ADC

DA[9:0]

AGC

RFAGC

Sigma

Delta

Modulator

I

40-Tap

Q

Equalizer Symbol Number

Pre-

Processor

Preproc Lock

Symbol Valid

FEC Lost Lock

Trellis

Decoder

Symbol Number

FEC

MPEG-2 Data

TSDISABLE

TSVALID

TSCLK

TSSYNC

TSLOCK

TSERR

INTRPTN

XTALI

30MHz

XTALO OSC

RESETn

Clock & Test

Control

JTAG

I2C bus

Register

Interface

RAM

Config

Data

3-Wire Bus

Interface

SCLK

SDATA

SEN0

SEN1

Fig. 2. Block Diagram

1. ADC

Input to the CXD1958Q is a single-ended IF signal centred at 36.125MHz. An integrated 8-bit ADC is clocked

at 30MHz and used to directly band-pass sample the IF signal. The 8-bit ADC is self biased by connecting

reference pins VRTS to VRT and reference pins VRBS to VRB. An option is provided to allow bypass of the

internal ADC if an external converter up to 10 bits is desired.

2. Pre-Processor and Equalizer

PRE-PROCESSOR

From ADC

digitised IF

IF to

Baseband

(ITB)

Image/

Decimation

Filters

Interpolator

Matched

Filter

To VGA

Automatic

Gain Control

Timing

Recovery

PLL

EQUALIZER

Decision

Feedback

Equalizer

DC

Correction

Decision

Device

To FEC

Differential

Decoder

Equalizer

Adaption

To Trellis

Decoder

Various Control

Signals

Carrier

Recovery

PLL

Fig. 3. Pre-Processor and Equalizer Block Diagram

–7–

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