MAX690 Просмотр технического описания (PDF) - Maxim Integrated
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MAX690 Datasheet PDF : 18 Pages
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MAX690–MAX695
Microprocessor Supervisory Circuits
Watchdog Timer
The microprocessor drives the WATCHDOG INPUT
(WDI) with an I/O line. When OSC IN and OSC SEL are
unconnected, the microprocessor must toggle the WDI
pin once every 1.6s to verify proper software execution. If
a hardware or software failure occurs such that WDI not
toggled the MAX691/MAX693 will issue a 50ms* RESET
pulse after 1.6s. This typically restarts the microproces-
sor’s power-up routine. A new RESET pulse is issued
every 1.6s until the WDI is again strobed.
The WATCHDOG OUTPUT (WDO) goes low if the
watchdog timer is not serviced within its timeout period.
Once WDO goes low it remains low until a transition
occurs at WDI. The watchdog timer feature can be dis-
abled by leaving WDI unconnected. OSC IN and OSC
SEL also allow other watchdog timing options, as shown
in Table 1 and Figure 8.
MAX690, MAX692, and MAX694
The 8 pin MAX690, MAX692, and MAX694 have most
of the features of the MAX691, MAX693, and MAX695.
Figure 2 shows the MAX690/MAX692/MAX694 in a typical
*200ms for MAX695
application. Operation is much the same as with the
MAX691/MAX693/MAX695 (Figure 1), but in this case, the
power- fail input (PFI) monitors the unregulated input to the
7805 regulator. The MAX690/MAX694 RESET output goes
low when VCC falls below 4.65V. The RESET output of the
MAX692 goes low when VCC drops below 4.4V.
The current consumption of the battery-backed-up power
bus must be less than 50mA. The MAX690/MAX692/
MAX694 does not have a BATT ON output to drive an
external transistor. The MAX690/MAX692/MAX694 also
does not include chip enable gating circuitry that is avail-
able on the MAX690/MAX692/MAX694. In many systems
though, CE gating is not needed since a low input to
the microprocessor RESET line prevents the processor
from writing to RAM during power-up and power-down
transients.
The MAX690/MAX692/MAX694 watchdog timer has a
fixed 1.6s timeout period. If WDI remains either low or
high for more than 1.6s, a RESET pulse is sent to the
microprocessor. The watchdog timer is disabled if WDI is
left unconnected.
POWER
MICRO-
+8V
7805
+5V
2
1 0.1µF
TO
PROCESSOR
3-TERMINAL
VCC
VOUT
CMOS
POWER
REGULATOR
0.1µF
MAX690
RAM
MAX692
MAX694
8
4
VBATT
MICROPROCESSOR
PFI
7
RESET
RESET
5
PFO
6
GND
WDI
NMI
I/O LINE
3
Figure 2. MAX690/692/694 Typical Application
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