TQ1089MC700 Просмотр технического описания (PDF) - TriQuint Semiconductor

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TQ1089MC700

11-Output Configurable Clock Buffer

TriQuint Semiconductor 

TQ1089

Functional Description

The core of the TQ1089 is a Phase-Locked Loop (PLL)

that continuously compares the reference clock

(REFCLK) to the feedback clock (FBIN), maintaining a

zero frequency difference between the two. Since one

of the outputs is always connected to FBIN, the PLL

keeps the propagation delay between the outputs and

the reference clock within –350 ps +500 ps for the

TQ1089–MC500, and within –350 ps +700 ps for the

TQ1089–MC700.

In the test mode, the PLL is bypassed and REFCLK is

connected directly to the Divide Logic block via the

MUX, as shown in Figure 1. This mode is useful for

debug and test purposes. The test mode is outlined

in Table 2.

The maximum rise and fall time at the output pins is 1.4

ns. All outputs of the TQ1089 are TTL-compatible with 30

mA symmetric drive and a minimum VOH of 2.4 V.

The internal Voltage-Controlled Oscillator (VCO), has an

operating range of 260 MHz to 360 MHz, as shown in

Table 1. The combination of the VCO and the Divide

Logic enables the TQ1089 to operate between 65 MHz

and 90 MHz and from 130 MHz to 180 MHz.

Power Up/Reset Synchronization

After power up or reset, the PLL requires time before it

achieves synchronization lock. The maximum time

required for synchronization (TSYNC) is 500 ms.

Table 1. Frequency Mode Selection

Output

Test

Feedback

Mode

0

Group B

÷2

0

Group A

÷4

Reference Clock

Frequency Range

130 MHz – 180 MHz

65 MHz – 90 MHz

Output Frequency Range

Group A: Q0–Q8

Group B: Q9,Q10

65 MHz – 90 MHz

65 MHz – 90 MHz

130 MHz – 180 MHz

130 MHz – 180 MHz

Table 2. Test Mode Selection

Test

Mode

1

÷2

Ref. Clock

f REF

Group A

Outputs Q0–Q8

f REF ÷ 4

Group B

Outputs Q9, Q10

f REF ÷ 2␣

2

For additional information and latest specifications, see our website: www.triquint.com

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