S-25A640B0A-T8T2U3 Просмотр технического описания (PDF) - Unspecified
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S-25A640B0A-T8T2U3 Datasheet PDF : 32 Pages
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Rev.3.2_02
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A640A, S-25A640B
2. S-25A640B
Table 21 Measurement Conditions
Input pulse voltage
Output reference voltage
Output load
0.2 VCC to 0.8 VCC
0.5 VCC
100 pF
Table 22
Ta = 40°C to 125°C
Item
Symbol
VCC = 2.5 V to 5.5 V
Unit
Min.
Max.
SCK clock frequency
fSCK
－
6.5
MHz
CS setup time during CS falling
tCSS.CL
65
－
ns
CS setup time during CS rising
tCSS.CH
65
－
ns
CS deselect time
tCDS
65
－
ns
CS hold time during CS falling
tCSH.CL
65
－
ns
CS hold time during CS rising
SCK clock time "H" *1
SCK clock time "L"*1
Rising time of SCK clock*2
Falling time of SCK clock*2
SI data input setup time
SI data input hold time
SCK "L" hold time during HOLD rising
tCSH.CH
65
tHIGH
65
tLOW
65
tRSK
－
tFSK
－
tDS
15
tDH
20
tSKH.HH
45
－
ns
－
ns
－
ns
1
s
1
s
－
ns
－
ns
－
ns
SCK "L" hold time during HOLD falling
tSKH.HL
30
－
ns
SCK "L" setup time during HOLD falling
tSKS.HL
0
－
ns
SCK "L" setup time during HOLD rising
tSKS.HH
0
Disable time of SO output*2
tOZ
－
Delay time of SO output
tOD
－
Hold time of SO output
Rising time of SO output*2
Falling time of SO output*2
tOH
0
tRO
－
tFO
－
Disable time of SO output during HOLD falling*2
tOZ.HL
－
Delay time of SO output during HOLD rising*2
tOD.HH
－
－
ns
75
ns
50
ns
－
ns
30
ns
30
ns
75
ns
50
ns
WP setup time
WP hold time
WP release / setup time
tWS1
tWH1
tWS2
0
－
ns
0
－
ns
0
－
ns
WP release / hold time
tWH2
20
－
ns
*1. The clock cycle of the SCK clock (frequency fSCK) is 1 / fSCK s. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.) tHIGH (min.) by minimizing
the SCK clock cycle time.
*2. These are values of sample and not 100% tested.
Item
Write time
Table 23
Ta = 40°C to 125°C
Symbol
VCC = 2.5 V to 5.5 V
Unit
Min.
Max.
tPR
－
5.0
ms
9
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