S-25A040A0A-K8T2UD Просмотр технического описания (PDF) - Unspecified
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S-25A040A0A-K8T2UD Datasheet PDF : 35 Pages
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Rev.5.2_02
FOR AUTOMOTIVE 125°C OPERATION SPI SERIAL E2PROM
S-25A010A/020A/040A
AC Electrical Characteristics
Table 14 Measurement Conditions
Input pulse voltage
Output reference voltage
Output load
0.2 VCC to 0.8 VCC
0.5 VCC
100 pF
Table 15
Item
Ta = 40°C to 125°C
Symbol VCC = 2.5 V to 5.5 V VCC = 3.0 V to 5.5 V VCC = 4.5 V to 5.5 V Unit
Min. Max. Min. Max. Min. Max.
SCK clock frequency
CS setup time during CS falling
fSCK
－
3.5
－
5.0
－
6.5 MHz
tCSS.CL
90
－
90
－
65
－
ns
CS setup time during CS rising
tCSS.CH
90
－
90
－
65
－
ns
CS deselect time
tCDS
160
－
140
－
110
－
ns
CS hold time during CS falling
tCSH.CL
90
－
90
－
65
－
ns
CS hold time during CS rising
SCK clock time "H"*1
SCK clock time "L"*1
Rising time of SCK clock*2
Falling time of SCK clock*2
SI data input setup time
SI data input hold time
SCK "L" hold time during HOLD rising
tCSH.CH
90
－
90
－
65
－
ns
tHIGH
125
－
95
－
65
－
ns
tLOW
125
－
95
－
65
－
ns
tRSK
－
1
－
1
－
1
s
tFSK
－
1
－
1
－
1
s
tDS
20
－
20
－
20
－
ns
tDH
30
－
30
－
30
－
ns
tSKH.HH
70
－
70
－
45
－
ns
SCK "L" hold time during HOLD falling
tSKH.HL
40
－
40
－
30
－
ns
SCK "L" setup time during HOLD falling
tSKS.HL
0
－
0
－
0
－
ns
SCK "L" setup time during HOLD rising
Disable time of SO output*2
tSKS.HH
0
－
0
－
0
tOZ
－
100
－
100
－
Delay time of SO output
tOD
－
120
－
90
－
Hold time of SO output
Rising time of SO output*2
Falling time of SO output*2
tOH
0
－
0
－
0
tRO
－
80
－
80
－
tFO
－
80
－
80
－
Disable time of SO output during HOLD falling*2 tOZ.HL
－
100
－
100
－
Delay time of SO output during HOLD rising*2
tOD.HH
－
80
－
80
－
－
ns
75
ns
60
ns
－
ns
50
ns
50
ns
75
ns
60
ns
WP setup time
tWS1
0
－
0
－
0
－
ns
WP hold time
tWH1
0
－
0
－
0
－
ns
WP release / setup time
tWS2
0
－
0
－
0
－
ns
WP release / hold time
tWH2
150
－
150
－
100
－
ns
*1. The clock cycle of the SCK clock (frequency fSCK) is 1 / fSCK s. This clock cycle is determined by a combination of
several AC characteristics. Note that the clock cycle cannot be set as (1 / fSCK) = tLOW (min.) tHIGH (min.) by minimizing
the SCK clock cycle time.
*2. These are values of sample and not 100% tested.
7
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