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CLRC632

Multiple Protocol Contactless Reader IC

Philips Electronics 

Philips Semiconductors

Multiple Protocol Contactless Reader IC

Product Specification Rev. 3.0; May 2003

CL RC632

3.2 Pin Description

Pin Types: I...Input; O...Output; PWR...Power

PIN SYMBOL TYPE

DESCRIPTION

1 OSCIN

I

Crystal Oscillator Input: input to the inverting amplifier of the oscillator.

This pin is also the input for an externally generated clock (fosc = 13.56 MHz).

2 IRQ

O Interrupt Request: output to signal an interrupt event

3 MFIN

I

MIFARE Interface Input: accepts a digital, serial data stream according to

ISO14443A (MIFARE)

42 MFOUT

MIFARE Interface Output: delivers a serial data stream according to ISO14443A

O

(MIFARE)

I•CODE Interface Output: delivers a serial data stream according to I•CODE1 and

ISO 15693

5 TX1

O Transmitter 1: delivers the modulated 13.56 MHz energy carrier

6 TVDD

PWR Transmitter Power Supply: supplies the output stage of TX1 and TX2

7 TX2

O Transmitter 2: delivers the modulated 13.56 MHz energy carrier

8 TVSS

PWR Transmitter Ground: supplies the output stage of TX1 and TX2

9 NCS

I Not Chip Select: selects and activates the µ-Processor interface of the CL RC632

NWR

101 R/NW

I Not Write: strobe to write data (applied on D0 to D7) into the CL RC632 register

I Read Not Write: selects if a read or write cycle shall be performed.

nWrite

I Not Write: selects if a read or write cycle shall be performed

NRD

111 NDS

I Not Read: strobe to read data from the CL RC632 register (applied on D0 to D7)

I Not Data Strobe: strobe for the read and the write cycle

nDStrb

I Not Data Strobe: strobe for the read and the write cycle

12 DVSS

PWR Digital Ground

13 D0

O Master In Slave Out (MISO), SPI interface,

13 D0 to D7

I/O 8 Bit Bi-directional Data Bus

…

201 AD0 to AD7 I/O 8 Bit Bi-directional Address and Data Bus

ALE

I

Address Latch Enable: signal to latch AD0 to AD5 into the internal address latch

when HIGH.

211 AS

nAStrb

I

Address Strobe: strobe signal to latch AD0 to AD5 into the internal address latch

when HIGH.

I

Not Address Strobe: strobe signal to latch AD0 to AD5 into the internal address latch

when LOW.

NSS

I Not Slave Select: strobe for the SPI communication

A0

I Address Line 0: Bit 0 of register address

221 nWait

O

Not Wait: signals with LOW that an access-cycle may started and with HIGH that it

may be finished.

MOSI

I Master Out Slave In, SPI interface

PIN Description (continued)

1 These pins offer different functionality according to the selected µ-Processor interface type. For detailed

information, refer to chapter 4.

2 The SL RC400 uses the name SIGOUT for the MFOUT pin. The CLRC 632 functionality includes the test possibilities

for the SL RC 400 using the pin MFOUT.

11

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