74ALVCH16601 Просмотр технического описания (PDF) - Nexperia B.V. All rights reserved
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74ALVCH16601 Datasheet PDF : 15 Pages
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Nexperia
74ALVCH16601
18-bit universal bus transceiver; 3-state
10.1. Waveforms and test circuit
Fig. 6.
VI
An, Bn
input
VM
VM
GND
VOH
Bn, An
output
tPHL
VM
tPLH
VM
VOL
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Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
The input An, Bn to output Bn, An propagation delays.
Fig. 7.
1/fmax
VI
LEBA, LEAB
CPBA, CPAB
input
VM
VM
VM
GND
tW
tPHL
tPLH
VOH
An, Bn
output
VM
VM
VOL
aaa-028857
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Latch enable input (LEAB, LEBA) and clock input (CPAB, CPBA) to output (Bn, An) propagation delays;
clock (CPAB, CPBA) pulse width and clock (CPAB, CPBA) maximum frequency
Fig. 8.
VI
OEAB, OEBA
input
VM
VM
GND
VCC
An, Bn output
LOW-to-OFF
OFF-to-LOW
VOL
tPLZ
VX
tPHZ
tPZL
VM
tPZH
VOH
An, Bn output
HIGH-to-OFF
OFF-to-HIGH
GND
VY
outputs
enabled
outputs
disabled
VM
outputs
enabled
aaa-028033
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
3-state enable and disable times.
74ALVCH16601
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 13 August 2018
© Nexperia B.V. 2018. All rights reserved
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