ADSP-TS101SAB1-100 Просмотр технического описания (PDF) - Analog Devices
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ADSP-TS101SAB1-100 Datasheet PDF : 48 Pages
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ADSP-TS101S
GLOBAL SPACE
0x FFFFFFFF
HOST
(MSH)
INTERNAL SPACE
0x 003 FFFFF
RE SERVE D
0 x0 03 00 00 0
0 x0 02 80 00 0
0 x0 02 00 00 0
INTERNAL REGISTERS (UREGS)
RE SERVE D
INTERNAL MEMORY 2
RE SERVE D
INTERNAL MEMORY 1
RE SERVE D
INTERNAL MEMORY 0
0x 001 80 7FF
0 x0 01 80 00 0
0 x0 01 0FFFF
0 x0 01 00 00 0
0 x0 00 8FFFF
0 x0 00 80 00 0
0 x0 00 0FFFF
0 x0 00 00 00 0
BANK 1
(MS1)
BANK 0
(MS0)
SDRAM
(MSSD)
PROCESSOR ID 7
PROCESSOR ID 6
PROCESSOR ID 5
PROCESSOR ID 4
PROCESSOR ID 3
PROCESSOR ID 2
PROCESSOR ID 1
PROCESSOR ID 0
BROADCAST
RES ERV ED
INTERNAL MEMORY
Figure 3. Memory Map
0 x1 00 000 00
0 x0 C00 00 00
0 x0 80 000 00
0 x0 40 000 00
0 x0 3C0 00 00
0 x0 38 000 00
0 x0 34 000 00
0 x0 30 000 00
0 x0 2C0 00 00
0 x0 28 000 00
0 x0 24 000 00
0 x0 20 000 00
0 x0 1C0 00 00
EACH IS A COPY
OF INTERNAL SPACE
0 x0 03 FFFFF
0 x0 00 000 00
EXTERNAL PORT
(OFF-CHIP MEMORY/PERIPHERALS INTERFACE)
The ADSP-TS101S processor’s external port provides the pro-
cessor’s interface to off-chip memory and peripherals. The
4G word address space is included in the DSP’s unified address
space. The separate on-chip buses—three 128-bit data buses and
three 32-bit address buses—are multiplexed at the external port
to create an external system bus with a single 64-bit data bus
and a single 32-bit address bus. The external port supports data
transfer rates of 800M bytes per second over external bus.
The external bus can be configured for 32- or 64-bit operation.
When the system bus is configured for 64-bit operation, the
lower 32 bits of the external data bus connect to even addresses,
and the upper 32 bits connect to odd addresses.
The external port supports pipelined, slow, and SDRAM proto-
cols. Addressing of external memory devices and memory-
mapped peripherals is facilitated by on-chip decoding of high-
order address lines to generate memory bank select signals.
The ADSP-TS101S provides programmable memory, pipeline
depth, and idle cycle for synchronous accesses, and external
acknowledge controls to support interfacing to pipelined or
slow devices, host processors, and other memory-mapped
peripherals with variable access, hold, and disable time
requirements.
Rev. C | Page 6 of 48 | May 2009
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