ADSP-TS101SAB2Z000 Просмотр технического описания (PDF) - Analog Devices

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ADSP-TS101SAB2Z000

TigerSHARC Embedded Processor

Analog Devices 

ADSP-TS101S

The ADSP-TS101S, in most cases, has a two-cycle arithmetic

execution pipeline that is fully interlocked, so whenever a com-

putation result is unavailable for another operation dependent

on it, the DSP automatically inserts one or more stall cycles as

needed. Efficient programming with dependency-free instruc-

tions can eliminate most computational and memory transfer

data dependencies.

CLOCK

REFERENCE

SDRAM

M EM ORY

(OPTIONAL)

CLK CS

ADDR RAS

DATA CAS

DQM

WE

CKE

A10

LINK

DEVICES

(4 MAX)

(OPTIONAL)

ADSP-TS101S

LCLK_P

SCLK_P

BMS

S/LCLK_N

VREF

LCLKRAT2–0

BRST

SCLKFREQ ADDR31–0

IRQ3–0

DATA63–0

FLAG3–0

ID2–0

MSSD

RAS

CAS

RD

WRH/WRL

ACK

MS1–0

LDQM

HDQM

SDWE

SDCKE

MSH

HBR

HBG

SDA10

FLYBY

IOEN

LXDAT7–0

LXCLKIN

LXCLKOUT

BR7–0

CPA

DPA

BOFF

DMAR3–0

LXDIR

TMR0E

BM

BUSLOCK

CONTROLIMP2–0

DS2–0

RESET JTAG

BOOT

EPROM

(OPTIONAL)

CS

ADDR

DATA

MEMORY

(OPTIONAL)

ADDR

DATA

OE

WE

ACK

CS

HOST

PROCESSOR

INTERFACE

(OPTIONAL)

ADDR

DATA

DMA DEVICE

(OPTIONAL)

DATA

Figure 2. Single-Processor System with External SDRAM

In addition, the ADSP-TS101S supports SIMD operations two

ways—SIMD compute blocks and SIMD computations. The

programmer can direct both compute blocks to operate on the

same data (broadcast distribution) or on different data (merged

distribution). In addition, each compute block can execute four

16-bit or eight 8-bit SIMD computations in parallel.

DUAL COMPUTE BLOCKS

The ADSP-TS101S has compute blocks that can execute com-

putations either independently or together as a SIMD engine.

The DSP can issue up to two compute instructions per compute

block each cycle, instructing the ALU, multiplier, or shifter to

perform independent, simultaneous operations.

The compute blocks are referred to as X and Y in assembly syn-

tax, and each block contains three computational units—an

ALU, a multiplier, a 64-bit shifter, and a 32-word register file.

• Register file—each compute block has a multiported

32-word, fully orthogonal register file used for transferring

data between the computation units and data buses and for

storing intermediate results. Instructions can access the

registers in the register file individually (word aligned), or

in sets of two (dual aligned) or four (quad aligned).

• ALU—the ALU performs a standard set of arithmetic oper-

ations in both fixed- and floating-point formats. It also

performs logic operations.

• Multiplier—the multiplier performs both fixed- and float-

ing-point multiplication and fixed-point multiply and

accumulate.

• Shifter—the 64-bit shifter performs logical and arithmetic

shifts, bit and bit stream manipulation, and field deposit

and extraction operations.

• Accelerator—128-bit unit for trellis decoding (for example,

Viterbi and turbo decoders) and complex correlations for

communication applications.

Using these features, the compute blocks can:

• Provide 8 MACs per cycle peak and 7.1 MACs per cycle

sustained 16-bit performance and provide 2 MACs per

cycle peak and 1.8 MACs per cycle sustained 32-bit perfor-

mance (based on FIR)

• Execute six single-precision, floating-point or execute 24

fixed-point (16-bit) operations per cycle, providing

1,800 MFLOPS or 7.3 GOPS performance

• Perform two complex 16-bit MACs per cycle

• Execute eight trellis butterflies in one cycle

DATA ALIGNMENT BUFFER (DAB)

The DAB is a quad word FIFO that enables loading of quad

word data from nonaligned addresses. Normally, load instruc-

tions must be aligned to their data size so that quad words are

loaded from a quad-aligned address. Using the DAB signifi-

cantly improves the efficiency of some applications, such as FIR

filters.

DUAL INTEGER ALUS (IALUS)

The ADSP-TS101S has two IALUs that provide powerful

address generation capabilities and perform many general-pur-

pose integer operations. Each of the IALUs:

• Provides memory addresses for data and update pointers

• Supports circular buffering and bit-reverse addressing

• Performs general-purpose integer operations, increasing

programming flexibility

• Includes a 31-word register file for each IALU

As address generators, the IALUs perform immediate or indi-

rect (pre- and post-modify) addressing. They perform modulus

and bit-reverse operations with no constraints placed on mem-

ory addresses for the modulus data buffer placement. Each

IALU can specify either a single, dual, or quad word access from

memory.

Rev. C | Page 4 of 48 | May 2009

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