ADSP-TS101SAB2-100 Просмотр технического описания (PDF) - Analog Devices

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производитель

ADSP-TS101SAB2-100

TigerSHARC Embedded Processor

Analog Devices 

ADSP-TS101S

SPECIFICATIONS

Note that component specifications are subject to change with-

out notice.

OPERATING CONDITIONS

Parameter

Test Conditions

Min

Typ

Max

Unit

VDD

Internal Supply Voltage

1.14

VDD_A

Analog Supply Voltage

1.14

VDD_IO I/O Supply Voltage

3.15

TCASE

Case Operating Temperature

–40

VIH

High Level Input Voltage1

@ VDD, VDD_IO = max

2

VIL

Low Level Input Voltage1

@ VDD, VDD_IO = min

–0.5

IDD

VDD Supply Current for Typical Activity2 @ CCLK = 250 MHz, VDD = 1.25 V,

1.2

TCASE = 25ºC

IDD

VDD Supply Current for Typical Activity2 @ CCLK = 300 MHz, VDD = 1.25 V,

1.5

TCASE = 25ºC

1.26

V

1.26

V

3.45

V

+85

ºC

VDD_IO + 0.5 V

+0.8

V

A

A

IDDIDLELP

IDD_IO

IDD_A

VDD Supply Current for IDLELP

Instruction Execution

VDD_IO Supply Current for Typical

Activity2

VDD_A Supply Current

@ CCLK = 300 MHz, VDD = 1.20 V,

TCASE = 25ºC

@ SCLK = 100 MHz, VDD_IO = 3.3 V,

TCASE = 25ºC

@ VDD = 1.25 V, TCASE = 25ºC

173

mA

137

mA

25

31.25

mA

VREF

Voltage Reference

1.4

1.6

V

1 Applies to input and bidirectional pins.

2 For details on internal and external power estimation, including: power vector definitions, current usage descriptions, and formulas, see EE-169, Estimating Power for the

ADSP-TS101S on the Analog Devices website—use site search on “EE-169” (www.analog.com). This document is updated regularly to keep pace with silicon revisions.

ELECTRICAL CHARACTERISTICS

Parameter

VOH

High Level Output Voltage1

VOL

Low Level Output Voltage1

IIH

High Level Input Current2

IIHP

High Level Input Current (pd)2

IIL

Low Level Input Current3

IILP

Low Level Input Current (pu)4

IOZH

Three-State Leakage Current High5, 6

IOZHP Three-State Leakage Current High (pd)7

IOZL

Three-State Leakage Current Low8

IOZLP

Three-State Leakage Current Low (pu)9

IOZLO Three-State Leakage Current Low (od)7

CIN

Input Capacitance10, 11

1 Applies to output and bidirectional pins.

2 Applies to input pins with internal pull-downs (pd).

3 Applies to input pins without internal pull-ups (pu).

4 Applies to input pins with internal pull-ups (pu).

5 Applies to three-stateable pins without internal pull-downs (pd).

6 Applies to open drain (od) pins with 500  pull-ups (pu).

7 Applies to three-stateable pins with internal pull-downs (pd).

8 Applies to three-stateable pins without internal pull-ups (pu).

9 Applies to three-stateable pins with internal pull-ups (pu).

10Applies to all signals.

11Guaranteed but not tested.

Test Conditions

@VDD_IO = min, IOH = –2 mA

@VDD_IO = min, IOL = 4 mA

@VDD_IO = max, VIN = VDD_IO max

@VDD_IO = max, VIN = VDD_IO max

@VDD_IO = max, VIN = 0 V

@VDD_IO = max, VIN = 0 V

@VDD_IO = max, VIN = VDD_IO max

@VDD_IO = max, VIN = VDD_IO max

@VDD_IO = max, VIN = 0 V

@VDD_IO = max, VIN = 0 V

@VDD_IO = max, VIN = 0 V

@fIN = 1 MHz, TCASE = 25ºC, VIN = 2.5 V

Min

Max

Unit

2.4

V

0.4

V

10

μA

17.2

44.5

μA

10

μA

–69

–23

μA

10

μA

17.2

44.5

μA

10

μA

–69

–23

μA

–9.8

–4.6

mA

5

pF

Rev. C | Page 20 of 48 | May 2009

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