ADSP-TS101S(RevA) Просмотр технического описания (PDF) - Analog Devices

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ADSP-TS101S
(Rev.:RevA)

TigerSHARC Embedded Processor

Analog Devices 

ADSP-TS101S

Clock Domains

As shown in Figure 4, the ADSP-TS101S has two clock inputs,

SCLK (system clock) and LCLK (local clock), that drive its

two major clock domains:

SCLK_P

DDLLLL

EXTERNAL INTERFACE

LCLK_P

DPLLL

CCLK

(INSTRUCTION RATE)

LCLKRATx

D/LLRL

LxCLKOUT/LxCLKIN

(LINK PORT RATE)

SPD BITS,

LCTLx REGISTER

Figure 4. Clock Domains

• SCLK (system clock). Provides clock input for the

external bus interface and defines the ac specification

reference for the external bus signals. The external bus

interface runs at 1× the SCLK frequency. A DLL locks

internal SCLK to SCLK input.

• LCLK (local clock). Provides clock input to the internal

clock driver, CCLK, which is the internal clock for the

core, internal buses, memory, and link ports. The instruc-

tion execution rate is equal to CCLK. A PLL from LCLK

generates CCLK which is phase-locked. The LCLKRAT

pins define the clock multiplication of LCLK to CCLK

(see Table 4). The link port clock is generated from

CCLK via a software programmable divisor. RESET

must be asserted until LCLK is stable and within speci-

fication for at least 2 ms. This applies to power-up as well

as any dynamic modification of LCLK after power-up.

Dynamic modification may include LCLK going out of

specification as long as RESET is asserted.

Connecting SCLK and LCLK to the same clock source is a

requirement for the device. Using an integer clock multipli-

cation value provides predictable cycle-by-cycle operation, a

requirement of fault-tolerant systems and some multi-

processing systems.

Noninteger values are completely functional and acceptable for

applications that do not require predictable cycle-by-cycle

operation.

Output Pin Drive Strength Control

Pins CONTROLIMP2-0 and DS2-0 work together to control

the output drive strength of two groups of pins, the

Address/Data/Control pin group and the Link pin group.

CONTROLIMP2-0 independently configures the two pin

groups to the maximum drive strength or to a digitally controlled

drive strength that is selectable by the DS2-0 pins (see Table 13

on Page 17). If the digitally controlled drive strength is selected

for a pin group the DS2-0 pins determine one of eight strength

levels for that group (see Table 14 on Page 17). The drive

strength selected varies the slew rate of the driver. Drive strength

0 (DS2-0 = 000) is the weakest and slowest slew rate. Drive

strength 7 (DS2-0 = 111) is the strongest and fastest slew rate.

CROSSCORE is a trademark of Analog Devices, Inc.

VisualDSP++ is a trademark of Analog Devices, Inc.

The stronger drive strengths are useful for high frequency

switching while the lower strengths may allow use of a relaxed

design methodology. The strongest drive strengths have a larger

di/dt and thus require more attention to signal integrity issues

such a ringing, reflections and coupling. Also a larger di/dt can

increase external supply rail noise, which impacts power supply

and power distribution design.

The drive strengths for the EMU, CPA, and DPA pins are not

controllable and are fixed to the maximum level.

For drive strength calculation, see Output Drive Currents on

Page 31.

Power Supplies

The ADSP-TS101S has separate power supply connections for

internal logic (VDD), analog circuits (VDD_A), and I/O buffer

(VDD_IO) power supply. The internal (VDD) and analog (VDD_A)

supplies must meet the 1.2 V requirement. The I/O buffer

(VDD_IO) supply must meet the 3.3 V requirement.

The analog supply (VDD_A) powers the clock generator PLLs. To

produce a stable clock, systems must provide a clean power

supply to power input VDD_A. Designs must pay critical attention

to bypassing the VDD_A supply.

The required power-on sequence for the DSP is to provide VDD

(and VDD_A) before VDD_IO.

Filtering Reference Voltage and Clocks

Figure 5 shows a possible circuit for filtering VREF, SCLK_N, and

LCLK_N. This circuit provides the reference voltage for the

switching voltage, system clock, and local clock references.

VDD_IO

R1

R2

C1

C2

VREF

SCLK_N

LCLK_N

VSS

R1: 2k⍀ SERIES RESISTOR

R2: 1.67k⍀ SERIES RESISTOR

C1: 1␮F CAPACITOR (SMD)

C2: 1nF CAPACITOR (HF SMD) PLACED CLOSE TO DSP’S PINS

Figure 5. VREF, SCLK_N, and LCLK_N Filter

Development Tools

The ADSP-TS101S is supported with a complete set of

CROSSCORE™ software and hardware development tools,

including Analog Devices emulators and VisualDSP++™ devel-

opment environment. The same emulator hardware that

supports other TigerSHARC processors also fully emulates the

ADSP-TS101S.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an algebraic

syntax), an archiver (librarian/library builder), a linker, a loader,

a cycle-accurate instruction-level simulator, a C/C++ compiler,

and a C/C++ runtime library that includes DSP and mathemat-

ical functions. A key point for these tools is C/C++ code

REV. A

–9–

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