ADSP-TS101S(RevA) Просмотр технического описания (PDF) - Analog Devices
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ADSP-TS101S Datasheet PDF : 44 Pages
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ADSP-TS101S
The Functional Block Diagram on Page 1 shows the ADSP-
TS101S processor’s architectural blocks. These blocks include:
• Dual compute blocks, each consisting of an ALU, multi-
plier, 64-bit shifter, and 32-word register file and
associated Data Alignment Buffers (DABs)
• Dual integer ALUs (IALUs), each with its own 31-word
register file for data addressing
• A program sequencer with Instruction Alignment Buffer
(IAB), Branch Target Buffer (BTB), and interrupt
controller
• Three 128-bit internal data buses, each connecting to one
of three 2M bit memory banks
• On-chip SRAM (6M bit)
• An external port that provides the interface to host pro-
cessors, multiprocessing space (DSPs), off-chip memory
mapped peripherals, and external SRAM and SDRAM
• A 14-channel DMA controller
• Four link ports
• Two 64-bit interval timers and timer expired pin
• A 1149.1 IEEE compliant JTAG test access port for
on-chip emulation
Figure 1 shows a typical single processor system with external
SDRAM. Figure 3 on Page 7 shows a typical multiprocessor
system.
CLOCK
REFERENCE
SDRAM
M EM ORY
(OPTIONAL)
CLK CS
ADDR RAS
DATA CAS
DQM
WE
CKE
A10
LINK
DEVICES
(4 MAX)
(OPTIONAL)
ADSP-TS101S
LCLK_P
SCLK_P
BMS
S/LCLK_N
VREF
LCLKRAT2–0
BRST
SCLKFREQ ADDR31–0
IRQ3–0
DATA63–0
FLAG3–0
ID2–0
MSSD
RAS
CAS
RD
WRH/WRL
ACK
MS1–0
LDQM
HDQM
SDWE
SDCKE
MSH
HBR
HBG
SDA10
FLYBY
IOEN
LXDAT7–0
LXCLKIN
LXCLKOUT
BR7–0
CPA
DPA
BOFF
DMAR3–0
LXDIR
TMR0E
BM
BUSLOCK
CONTROLIMP2–0
DS2–0
RESET JTAG
BOOT
EPROM
(OPTIONAL)
CS
ADDR
DATA
MEMORY
(OPTIONAL)
ADDR
DATA
OE
WE
ACK
CS
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ADDR
DATA
DMA DEVICE
(OPTIONAL)
DATA
Figure 1. Single Processor System with External SDRAM
Static Superscalar is a trademark of Analog Devices, Inc.
The TigerSHARC processor uses a Static Superscalar™ archi-
tecture. This architecture is superscalar in that the ADSP-
TS101S processor’s core can execute simultaneously from one
to four 32-bit instructions encoded in a Very Large Instruction
Word (VLIW) instruction line using the DSP’s dual compute
blocks. Because the DSP does not perform instruction reordering
at runtime—the programmer selects which operations will
execute in parallel prior to runtime—the order of instructions is
static.
With few exceptions, an instruction line, whether it contains one,
two, three, or four 32-bit instructions, executes with a throughput
of one cycle in an eight-deep processor pipeline.
For optimal DSP program execution, programmers must follow
the DSP’s set of instruction parallelism rules when encoding an
instruction line. In general, the selection of instructions that the
DSP can execute in parallel each cycle depends on the instruction
line resources each instruction requires and on the source and
destination registers used in the instructions. The programmer
has direct control of three core components—the IALUs, the
compute blocks, and the program sequencer.
The ADSP-TS101S, in most cases, has a two-cycle arithmetic
execution pipeline that is fully interlocked, so whenever a com-
putation result is unavailable for another operation dependent on
it, the DSP automatically inserts one or more stall cycles as
needed. Efficient programming with dependency-free instruc-
tions can eliminate most computational and memory transfer
data dependencies.
In addition, the ADSP-TS101S supports SIMD operations two
ways—SIMD compute blocks and SIMD computations.The
programmer can direct both compute blocks to operate on the
same data (broadcast distribution) or on different data (merged
distribution). In addition, each compute block can execute four
16-bit or eight 8-bit SIMD computations in parallel.
Dual Compute Blocks
The ADSP-TS101S has compute blocks that can execute com-
putations either independently or together as a SIMD engine.
The DSP can issue up to two compute instructions per compute
block each cycle, instructing the ALU, multiplier, or shifter to
perform independent, simultaneous operations.
The compute blocks are referred to as X and Y in assembly
syntax, and each block contains three computational units—an
ALU, a multiplier, a 64-bit shifter—and a 32-word register file.
• Register File—Each compute block has a multiported
32-word, fully orthogonal register file used for transfer-
ring data between the computation units and data buses
and for storing intermediate results. Instructions can
access the registers in the register file individually (word
aligned), or in sets of two (dual aligned) or four (quad
aligned).
• ALU—The ALU performs a standard set of arithmetic
operations in both fixed- and floating-point formats. It
also performs logic operations.
• Multiplier—The multiplier performs both fixed- and
floating-point multiplication and fixed-point multiply and
accumulate.
REV. A
–3–
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