ADSP-21368SKBPZENG Просмотр технического описания (PDF) - Analog Devices

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ADSP-21368SKBPZENG

SHARC® Processor

Analog Devices 

Preliminary Technical Data

Multiple processors can share the external bus with no addi-

tional arbitration logic. Arbitration logic is included on-chip to

allow the connection of up to four processors.

Bus arbitration is accomplished through the BR1-4 signals and

the priority scheme for bus arbitration is determined by the set-

ting of the RPBA pin. Table 3 on page 12 provides descriptions

of the pins used in multiprocessor systems.

ADSP-21368 INPUT/OUTPUT FEATURES

The ADSP-21368 I/O processor provides 34 channels of DMA,

as well as an extensive set of peripherals. These include a 20 pin

Digital Audio Interface which controls:

• Eight Serial ports

• S/PDIF Receiver/Transmitter

• Four Precision Clock generators

• Four Sample Rate Converters

• Internal Data port/Parallel Data Acquisition port

The ADSP-21368 processor also contains a 14 pin Digital

Peripheral Interface which controls:

• Three general-purpose timers

• Two Serial Peripheral Interfaces

• Two Universal Asynchronous Receiver/Transmitters

(UARTs)

• A Two Wire Interface/I2C

DMA Controller

The ADSP-21368’s on-chip DMA controller allows data trans-

fers without processor intervention. The DMA controller

operates independently and invisibly to the processor core,

allowing DMA operations to occur while the core is simulta-

neously executing its program instructions. DMA transfers can

occur between the ADSP-21368’s internal memory and its serial

ports, the SPI-compatible (Serial Peripheral Interface) ports, the

IDP (Input Data Port), the Parallel Data Acquisition Port

(PDAP) or the UART. Thirty-four channels of DMA are avail-

able on the ADSP-21368—sixteen via the serial ports, eight via

the Input Data Port, four for the UARTs, two for the SPI inter-

face, two for the external port, and two for memory-to-memory

transfers. Programs can be downloaded to the ADSP-21368

using DMA transfers. Other DMA features include interrupt

generation upon completion of DMA transfers, and DMA

chaining for automatic linked DMA transfers.

Delay Line DMA

The ADSP-21368 processor provides Delay Line DMA func-

tionality. This allows processor reads and writes to external

Delay Line Buffers (and hence to external memory) with limited

core interaction.

Digital Audio Interface (DAI)

The Digital Audio Interface (DAI) provides the ability to con-

nect various peripherals to any of the DSPs DAI pins

(DAI_P20–1).

ADSP-21368

Programs make these connections using the Signal Routing

Unit (SRU, shown in TBD).

The SRU is a matrix routing unit (or group of multiplexers) that

enables the peripherals provided by the DAI to be intercon-

nected under software control. This allows easy use of the DAI

associated peripherals for a much wider variety of applications

by using a larger set of algorithms than is possible with non con-

figurable signal paths.

The DAI also includes eight serial ports, an S/PDIF

receiver/transmitter, four precision clock generators (PCG),

eight channels of synchronous sample rate converters, and an

input data port (IDP). The IDP provides an additional input

path to the ADSP-21368 core, configurable as either eight chan-

nels of I2S serial data or as seven channels plus a single 20-bit

wide synchronous parallel data acquisition port. Each data

channel has its own DMA channel that is independent from the

ADSP-21368's serial ports.

For complete information on using the DAI, see the ADSP-

2136x SHARC Processor Hardware Reference.

Serial Ports

The ADSP-21368 features eight synchronous serial ports that

provide an inexpensive interface to a wide variety of digital and

mixed-signal peripheral devices such as Analog devices AD183x

family of audio codecs, ADCs, and DACs. The serial ports are

made up of two data lines, a clock and frame sync. The data

lines can be programmed to either transmit or receive and each

data line has a dedicated DMA channel.

Serial ports are enabled via 16 programmable and simultaneous

receive or transmit pins that support up to 32 transmit or 32

receive channels of audio data when all eight SPORTS are

enabled, or eight full duplex TDM streams of 128 channels per

frame.

The serial ports operate at a maximum data rate of 50M bits/s.

Serial port data can be automatically transferred to and from

on-chip memory via dedicated DMA channels. Each of the

serial ports can work in conjunction with another serial port to

provide TDM support. One SPORT provides two transmit sig-

nals while the other SPORT provides the two receive signals.

The frame sync and clock are shared.

Serial ports operate in five modes:

• Standard DSP serial mode

• Multichannel (TDM) mode with support for Packed I2S

mode

• I2S mode

• Packed I2S mode

• Left-justified sample pair mode

Left-justified sample pair mode is a mode where in each frame

sync cycle two samples of data are transmitted/received—one

sample on the high segment of the frame sync, the other on the

low segment of the frame sync. Programs have control over var-

ious attributes of this mode.

Rev. PrA | Page 7 of 48 | November 2004

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