ADSP-BF539WYBCZ-4A Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

производитель

ADSP-BF539WYBCZ-4A

Blackfin® Embedded Processor

Analog Devices 

Preliminary Technical Data

Table 3. System and Core Event Mapping (Continued)

Event Source

DMA13 Interrupt (SPORT2 TX)

DMA14 Interrupt (SPORT3 RX)

DMA15 Interrupt (SPORT3 TX)

DMA5 Interrupt (SPI0)

DMA18 Interrupt (SPI1)

DMA19 Interrupt (SPI2)

DMA6 Interrupt (UART0 RX)

DMA7 Interrupt (UART0 TX)

DMA20 Interrupt (UART1 RX)

DMA21 Interrupt (UART1 TX)

DMA22 Interrupt (UART2 RX)

DMA23 Interrupt (UART2 TX)

Timer0, Timer1, Timer2 Interrupts

TWI0 Interrupt

TWI1 Interrupt

CAN Receive Interrupt

CAN Transmit Interrupt

MXVR Status Interrupt

MXVR Control Message Interrupt

MXVR Asynchronous Packet Interrupt

Programmable Flags Interrupt

MDMA0 Stream 0 Interrupt

MDMA0 Stream 1 Interrupt

MDMA1 Stream 0 Interrupt

MDMA1 Stream 1 Interrupt

Software Watchdog Timer

Core

Event Name

IVG9

IVG9

IVG9

IVG10

IVG10

IVG10

IVG10

IVG10

IVG10

IVG10

IVG10

IVG10

IVG11

IVG11

IVG11

IVG11

IVG11

IVG11

IVG11

IVG11

IVG12

IVG13

IVG13

IVG13

IVG13

IVG13

register may be read while in supervisor mode and may

only be written while in supervisor mode when the corre-

sponding IMASK bit is cleared.

• CEC Interrupt Mask Register (IMASK) – The IMASK reg-

ister controls the masking and unmasking of individual

events. When a bit is set in the IMASK register, that event is

unmasked and will be processed by the CEC when asserted.

A cleared bit in the IMASK register masks the event, pre-

venting the processor from servicing the event even though

the event may be latched in the ILAT register. This register

may be read or written while in supervisor mode. (Note

that general purpose interrupts can be globally enabled and

disabled with the STI and CLI instructions, respectively.)

• CEC Interrupt Pending Register (IPEND) – The IPEND

register keeps track of all nested events. A set bit in the

IPEND register indicates the event is currently active or

nested at some level. This register is updated automatically

by the controller but may be read while in supervisor mode.

ADSP-BF539/ADSP-BF539F

The SIC allows further control of event processing by providing

three 32-bit interrupt control and status registers. Each register

contains a bit corresponding to each of the peripheral interrupt

events shown in Table 3 on Page 8.

• SIC Interrupt Mask Registers (SIC_IMASKx)– These regis-

ters control the masking and unmasking of each peripheral

interrupt event. When a bit is set in these registers, that

peripheral event is unmasked and will be processed by the

system when asserted. A cleared bit in these registers masks

the peripheral event, preventing the processor from servic-

ing the event.

• SIC Interrupt Status Registers (SIC_ISRx) – As multiple

peripherals can be mapped to a single event, these registers

allow the software to determine which peripheral event

source triggered the interrupt. A set bit indicates the

peripheral is asserting the interrupt, and a cleared bit indi-

cates the peripheral is not asserting the event.

• SIC Interrupt Wakeup Enable Registers (SIC_IWRx) – By

enabling the corresponding bit in these registers, a periph-

eral can be configured to wake up the processor, should the

core be idled when the event is generated. (For more infor-

mation, see Dynamic Power Management on Page 14.)

Because multiple interrupt sources can map to a single general

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC will recognize and queue the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the state of the processor.

DMA CONTROLLERS

The ADSP-BF539/ADSP-BF539F processor has multiple, inde-

pendent DMA controllers that support automated data transfers

with minimal overhead for the processor core. DMA transfers

can occur between the ADSP-BF539/ADSP-BF539F processor

internal memories and any of its DMA capable peripherals.

Additionally, DMA transfers can be accomplished between any

of the DMA capable peripherals and external devices connected

to the external memory interfaces, including the SDRAM con-

troller and the asynchronous memory controller. DMA capable

peripherals include the SPORTs, SPI port, UART, and PPI. Each

individual DMA capable peripheral has at least one dedicated

DMA channel. The MXVR peripheral has its own dedicated

DMA controller, which supports its own unique set of operating

modes.

Rev. PrF | Page 9 of 68 | September 2006

Share Link: