ADSP-BF539WYBCZ-4A Просмотр технического описания (PDF) - Analog Devices

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ADSP-BF539WYBCZ-4A

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF539/ADSP-BF539F

• Non-Maskable Interrupt (NMI) – The NMI event can be

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly shut-

down of the system.

• Exceptions – Events that occur synchronously to program

flow (i.e., the exception will be taken before the instruction

is allowed to complete). Conditions such as data alignment

violations and undefined instructions cause exceptions.

• Interrupts – Events that occur asynchronously to program

flow. They are caused by input pins, timers, and other

peripherals, as well as by an explicit software instruction.

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, the state of the processor is saved on the

supervisor stack.

The ADSP-BF539/ADSP-BF539F processor Event Controller

consists of two stages, the Core Event Controller (CEC) and the

System Interrupt Controller (SIC). The Core Event Controller

works with the System Interrupt Controller to prioritize and

control all system events. Conceptually, interrupts from the

peripherals enter into the SIC, and are then routed directly into

the general purpose interrupts of the CEC.

Core Event Controller (CEC)

The CEC supports nine general purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general purpose interrupts, the two lowest priority inter-

rupts (IVG15–14) are recommended to be reserved for software

interrupt handlers, leaving seven prioritized interrupt inputs to

support the peripherals of the ADSP-BF539/ADSP-BF539F pro-

cessor. Table 2 describes the inputs to the CEC, identifies their

names in the Event Vector Table (EVT), and lists their

priorities.

System Interrupt Controller (SIC)

The System Interrupt Controller provides the mapping and

routing of events from the many peripheral interrupt sources to

the prioritized general purpose interrupt inputs of the CEC.

Although the ADSP-BF539/ADSP-BF539F processor provides a

default mapping, the user can alter the mappings and priorities

of interrupt events by writing the appropriate values into the

Interrupt Assignment Registers (SIC_IARx). Table 3 describes

the inputs into the SIC and the default mappings into the CEC.

Event Control

The ADSP-BF539/ADSP-BF539F processor provides the user

with a very flexible mechanism to control the processing of

events. In the CEC, three registers are used to coordinate and

control events. Each register is 16 bits wide:

• CEC Interrupt Latch Register (ILAT) – The ILAT register

indicates when events have been latched. The appropriate

bit is set when the processor has latched the event and

cleared when the event has been accepted into the system.

This register is updated automatically by the controller, but

it may also be written to clear (cancel) latched events. This

Preliminary Technical Data

Table 2. Core Event Controller (CEC)

Priority

(0 is Highest)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Event Class

Emulation/Test Control

Reset

Non-Maskable Interrupt

Exception

Reserved

Hardware Error

Core Timer

General Interrupt 7

General Interrupt 8

General Interrupt 9

General Interrupt 10

General Interrupt 11

General Interrupt 12

General Interrupt 13

General Interrupt 14

General Interrupt 15

Table 3. System and Core Event Mapping

Event Source

PLL Wakeup Interrupt

DMA Controller 0 Error

DMA Controller 1 Error

PPI Error Interrupt

SPORT0 Error Interrupt

SPORT1 Error Interrupt

SPORT2 Error Interrupt

SPORT3 Error Interrupt

MXVR Synchronous Data Interrupt

SPI0 Error Interrupt

SPI1 Error Interrupt

SPI2 Error Interrupt

UART0 Error Interrupt

UART1 Error Interrupt

UART2 Error Interrupt

CAN Error Interrupt

Real Time Clock Interrupts

DMA0 Interrupt (PPI)

DMA1 Interrupt (SPORT0 RX)

DMA2 Interrupt (SPORT0 TX)

DMA3 Interrupt (SPORT1 RX)

DMA4 Interrupt (SPORT1 TX)

DMA12 Interrupt (SPORT2 RX)

EVT Entry

EMU

RST

NMI

EVX

—

IVHW

IVTMR

IVG7

IVG8

IVG9

IVG10

IVG11

IVG12

IVG13

IVG14

IVG15

Core

Event Name

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG7

IVG8

IVG8

IVG9

IVG9

IVG9

IVG9

IVG9

Rev. PrF | Page 8 of 68 | September 2006

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