ADSP-BF539WYBCZ4F8 Просмотр технического описания (PDF) - Analog Devices

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ADSP-BF539WYBCZ4F8

Blackfin® Embedded Processor

Analog Devices 

Preliminary Technical Data

0xFFFF FFFF

0xFFE0 0000

0xFFC0 0000

0xFFB0 1000

0xFFB0 0000

0xFFA1 4000

0xFFA1 0000

0xFFA0 0000

0xFF90 8000

0xFF90 4000

0xFF90 0000

0xFF80 8000

0xFF80 4000

0xFF80 0000

0xEF00 0000

0x2040 0000

0x2030 0000

0x2020 0000

0x2010 0000

0x2000 0000

0x0800 0000

0x0000 0000

CORE MMR REGISTERS (2M BYTE)

SYSTEM MMR REGISTERS (2M BYTE)

RESERVED

SCRATCHPAD SRAM (4K BYTE)

RESERVED

INSTRUCTION SRAM / CACHE (16K BYTE)

INSTRUCTION SRAM (64K BYTE)

RESERVED

DATA BANK B SRAM / CACHE (16K BYTE)

DATA BANK B SRAM (16K BYTE)

RESERVED

DATA BANK A SRAM / CACHE (16K BYTE)

DATA BANK A SRAM (16K BYTE)

RESERVED

RESERVED

ASYNC MEMORY BANK 3 (1M BYTE) OR

ON-CHIP FLASH

ASYNC MEMORY BANK 2 (1M BYTE) OR

ON-CHIP FLASH

ASYNC MEMORY BANK 1 (1M BYTE) OR

ON-CHIP FLASH

ASYNC MEMORY BANK 0 (1M BYTE) OR

ON-CHIP FLASH

RESERVED

SDRAM MEMORY (16M BYTE - 128M BYTE)

Figure 3. ADSP-BF539/ADSP-BF539F Internal/External Memory Map

ADDR19-1

ARE

AWE

ARDY

DATA15-0

GND

VDDEXT

AMS3-0

RESET

ADSP-BF539F

package

A18-0

OE

WE

RY/BY

DQ15-0

VSS

VCC

BYTE

CE

RESET

Figure 4. Internal Connection of Flash Memory

The flash chip enable pin FCE must be connected to AMS0 or

AMS3–1 through a printed circuit board trace. When connected

to AMS0, the Blackfin processor can boot from the flash die.

ADSP-BF539/ADSP-BF539F

When connected to AMS3–1, the flash memory will appear as

non-volatile memory in the processor memory map shown in

Figure 3 on Page 7.

Flash Memory Programming

The ADSP-BF539F4 and ADSP-BF539F8 flash memory may be

programmed before or after mounting on the printed circuit

board.

To program the flash prior to mounting on the printed circuit

board, use a hardware programming tool that can provide the

data, address, and control stimuli to the flash die through the

external pins on the package. During this programming, VDDEXT

and GND must be provided to the package and the Blackfin

must be held in reset with bus request (BR) asserted and a

CLKIN provided.

The VisualDSP++® tools may be used to program the flash

memory after the device is mounted on a printed circuit board.

Flash Memory Sector Protection

To use the sector protection feature, a high voltage (+12 V nom-

inal) must be applied to the flash FRESET pin. Refer to the flash

datasheet for details.

I/O Memory Space

Blackfin processors do not define a separate I/O space. All

resources are mapped through the flat 32-bit address space. On-

chip I/O devices have their control registers mapped into mem-

ory mapped registers (MMRs) at addresses near the top of the

4G byte address space. These are separated into two smaller

blocks, one which contains the control MMRs for all core func-

tions, and the other which contains the registers needed for

setup and control of the on-chip peripherals outside of the core.

The MMRs are accessible only in supervisor mode and appear

as reserved space to on-chip peripherals.

Booting

The ADSP-BF539/ADSP-BF539F processor contains a small

boot kernel, which configures the appropriate peripheral for

booting. If the ADSP-BF539/ADSP-BF539F processor is config-

ured to boot from boot ROM memory space, the processor

starts executing from the on-chip boot ROM. For more infor-

mation, see Booting Modes on Page 17.

Event Handling

The event controller on the ADSP-BF539/ADSP-BF539F pro-

cessor handles all asynchronous and synchronous events to the

processor. The ADSP-BF539/ADSP-BF539F processor provides

event handling that supports both nesting and prioritization.

Nesting allows multiple event service routines to be active

simultaneously. Prioritization ensures that servicing of a higher

priority event takes precedence over servicing of a lower priority

event. The controller provides support for five different types of

events:

• Emulation – An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

• Reset – This event resets the processor.

Rev. PrF | Page 7 of 68 | September 2006

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