ADSP-BF539(RevA) Просмотр технического описания (PDF) - Analog Devices
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ADSP-BF539 Datasheet PDF : 60 Pages
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next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the general-
purpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depend-
ing on the activity within and the state of the processor.
DMA CONTROLLERS
The ADSP-BF539/ADSP-BF539F processor has multiple, inde-
pendent DMA controllers that support automated data transfers
with minimal overhead for the processor core. DMA transfers
can occur between the ADSP-BF539/ADSP-BF539F processor
internal memories and any of its DMA capable peripherals.
Additionally, DMA transfers can be accomplished between any
of the DMA-capable peripherals and external devices connected
to the external memory interfaces, including the SDRAM con-
troller and the asynchronous memory controller. DMA capable
peripherals include the SPORTs, SPI ports, UARTs, and PPI.
Each individual DMA capable peripheral has at least one dedi-
cated DMA channel. In addition, the MXVR peripheral has its
own dedicated DMA controller, which supports its own unique
set of operating modes.
The ADSP-BF539/ADSP-BF539F processor DMA controllers
support both 1-dimensional (1-D) and 2-dimensional (2-D)
DMA transfers. DMA transfer initialization can be imple-
mented from registers or from sets of parameters called
descriptor blocks.
The 2-D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements and arbitrary row and
column step sizes up to ±32K elements. Furthermore, the col-
umn step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be
deinterleaved on the fly.
Examples of DMA types supported by the ADSP-BF539/ADSP-
BF539F processors DMA controller include:
• A single, linear buffer that stops upon completion
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
• 1-D or 2-D DMA using a linked list of descriptors
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, there are
four memory DMA channels provided for transfers between the
various memories of the ADSP-BF539/ADSP-BF539F processor
system. This enables transfers of blocks of data between any of
the memories—including external SDRAM, ROM, SRAM, and
flash memory—with minimal processor intervention. Memory
DMA transfers can be controlled by a very flexible descriptor-
based methodology or by a standard register-based autobuffer
mechanism.
REAL-TIME CLOCK
The ADSP-BF539/ADSP-BF539F processor real-time clock
(RTC) provides a robust set of digital watch features, including
current time, stopwatch, and alarm. The RTC is clocked by a
ADSP-BF539/ADSP-BF539F
32.768 kHz crystal external to the ADSP-BF539/ADSP-BF539F
processors. The RTC peripheral has dedicated power supply
pins so that it can remain powered up and clocked even when
the rest of the processor is in a low power state. The RTC pro-
vides several programmable interrupt options, including
interrupt per second, minute, hour, or day clock ticks, interrupt
on programmable stopwatch countdown, or interrupt at a pro-
grammed alarm time.
The 32.768 kHz input clock frequency is divided down to a 1 Hz
signal by a prescaler. The counter function of the timer consists
of four counters: a 60-second counter, a 60-minute counter, a
24-hour counter, and an 32,768-day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: the first alarm is
for a time of day. The second alarm is for a day and time of
that day.
The stopwatch function counts down from a programmed
value, with one second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the ADSP-
BF539/ADSP-BF539F processor from sleep mode upon genera-
tion of any RTC wake-up event. Additionally, an RTC wake-up
event can wake up the ADSP-BF539/ADSP-BF539F processor
from deep sleep mode, and wake up the on-chip internal voltage
regulator from a powered down state.
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 5.
RTXI
RTXO
R1
X1
C1
C2
SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12 pF LOAD (SURFACE-MO UNT PACKAGE)
C1 = 22pF
C2 = 22pF
R1 = 10MΩ
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECI FIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFI CATIONS ASSUME BOARD TRACE CAPACITANCE OF 3pF.
Figure 5. External Components for RTC
WATCHDOG TIMER
The ADSP-BF539/ADSP-BF539F processors include a 32-bit
timer that can be used to implement a software watchdog func-
tion. A software watchdog can improve system availability by
forcing the processor to a known state through generation of a
hardware reset, nonmaskable interrupt (NMI), or general-pur-
pose interrupt, if the timer expires before being reset by
software. The programmer initializes the count value of the
Rev. A | Page 9 of 60 | February 2008
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