ADSP-BF539(RevA) Просмотр технического описания (PDF) - Analog Devices
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ADSP-BF539 Datasheet PDF : 60 Pages
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Booting
The ADSP-BF539/ADSP-BF539F processor contains a small
boot kernel, which configures the appropriate peripheral for
booting. If the ADSP-BF539/ADSP-BF539F processor is config-
ured to boot from boot ROM memory space, the processor
starts executing from the on-chip boot ROM. For more infor-
mation, see Booting Modes on Page 16.
Event Handling
The event controller on the ADSP-BF539/ADSP-BF539F pro-
cessor handles all asynchronous and synchronous events to the
processor. The ADSP-BF539/ADSP-BF539F processor provides
event handling that supports both nesting and prioritization.
Nesting allows multiple event service routines to be active
simultaneously. Prioritization ensures that servicing of a higher
priority event takes precedence over servicing of a lower priority
event. The controller provides support for five different types of
events:
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset – This event resets the processor.
• Nonmaskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
• Exceptions – Events that occur synchronously to program
flow (i.e., the exception will be taken before the instruction
is allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
The ADSP-BF539/ADSP-BF539F processor’s event controller
consists of two stages, the core event controller (CEC) and the
system interrupt controllers (SIC). The core event controller
works with the system interrupt controllers to prioritize and
control all system events. Conceptually, interrupts from the
peripherals enter into one of the SIC, and are then routed
directly into the general-purpose interrupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF539/ADSP-BF539F pro-
cessors. Table 2 describes the inputs to the CEC, identifies their
names in the event vector table (EVT), and lists their priorities.
ADSP-BF539/ADSP-BF539F
Table 2. Core Event Controller (CEC)
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Event Class
Emulation/Test Control
Reset
Nonmaskable Interrupt
Exception
Reserved
Hardware Error
Core Timer
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
EVT Entry
EMU
RST
NMI
EVX
—
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
System Interrupt Controllers (SIC)
The system interrupt controllers (SIC0, SIC1) provide the map-
ping and routing of events from the many peripheral interrupt
sources to the prioritized general-purpose interrupt inputs of
the CEC. Although the ADSP-BF539/ADSP-BF539F processors
provide a default mapping, the user can alter the mappings and
priorities of interrupt events by writing the appropriate values
into the interrupt assignment registers (SIC_IARx). Table 3
describes the inputs into the SICs and the default mappings into
the CEC.
Table 3. System and Core Event Mapping
Event Source
PLL Wake-up Interrupt
DMA Controller 0 Error
DMA Controller 1 Error
PPI Error Interrupt
SPORT0 Error Interrupt
SPORT1 Error Interrupt
SPORT2 Error Interrupt
SPORT3 Error Interrupt
MXVR Synchronous Data Interrupt
SPI0 Error Interrupt
SPI1 Error Interrupt
SPI2 Error Interrupt
UART0 Error Interrupt
UART1 Error Interrupt
Core
Event Name
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
Rev. A | Page 7 of 60 | February 2008
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