78P2241-IGT Просмотр технического описания (PDF) - TDK Corporation
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78P2241-IGT Datasheet PDF : 23 Pages
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78P2241
E3/DS3/STS-1
Transceiver
PIN DESCRIPTION: The 28-pin PLCC is compatible with 78P7200
NAME
LIN+
LIN-
RCLK
RPOS/
RNRZ
RNEG
LOS
LOUT+
LOUT-
TCLK
TPOS/
TNRZ
TNEG
LBO
E#
TXEN
MON
ICKP
LPBK
VCC
PIN
TQFP
42
44
33
35
34
39
9
11
18
16
17
13
15
22
28
10
40
5,6,20,
21,37,38
PIN
PLCC
1
3
23
25
24
27
9
11
16
14
15
12
13
18
21
10
28
7,17,26
TYPE DESCRIPTION
I
Line Input: Differential AMI inputs to the chip. Should be
transformer coupled and terminated at 75-ohm resistor.
O Receive Clock: Recovered receive clock.
O Receive Positive Data / NRZ Data: When ENDEC is high,
this pin indicates reception of a positive AMI pulse on the
coax cable. When ENDEC is low, it outputs decoded NRZ
data.
O Receive Negative Data: When ENDEC is high, this pin indicates
reception of a negative AMI pulse on the coax. When ENDEC is
low this pin is at logic low.
O Loss of Signal: logic low indicates that receiver signal (LIN±)
is below the threshold level. RPOS and RNEG are forced
low when LOS=0.
O Line Out: Differential AMI Output. Requires a 2:1 center
tapped transformer and 301Ω resistor.
I
Transmitter Clock Input: This signal is used to latch the
TPOS/TNRZ and TNEG signals into the 78P2241.
I
Transmit Positive Data / Transmit NRZ: When ENDEC is
high, a logic one on this pin generates a positive AMI pulse
on the coax. This pin should not be high at the same time
that TNEG is high.
When ENDEC is low, data on this pin is encoded and
converted into positive and negative AMI pulses.
I
Transmit Negative Data: When ENDEC is high, a logic one on
this pin generates a negative AMI pulse on the coax. This pin
should not be high at the same time that TPOS/TNRZ is high.
When ENDEC is low, this pin is ignored.
I
Line Build-Out, Transmitter: Logic low used with 225ft or
more of cable is used on transmit path. Logic high used with
less than 225ft of cable.
I3 DS3, E3 and STS-1 Select: Set low for E# applications. Set
high for DS3, allow to float for STS-1 operation. Formerly
OPT! on the 78P7200.
I
Transmitter Enable: When high, enables transmitter. When
low, tri-states transmitter drivers, LOUT±. This pin was
called OPT@ on 78P7200.
I
DSX3 / E3 Monitor Select: When set high, an additional 20-
dB gain stage is added to the receiver gain. This pin was
tied to GND on the 78P7200.
I3 Invert Clock Polarity: When low, the polarities of RCLK and
TCLK are the same as those on the 78P7200. When set high,
the polarity of TCLK is inverted. When allowed to float, the
polarities of both RCLK and TCLK are inverted.
I3 Loop-back Select: When high, neither loop-back is activated.
When allowed to float RPOS, RNEG and RCLK are looped
back onto TPOS, TNEG and TCLK. When low, LOUT± is
looped back onto LIN±.
P Power Supply.
4
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