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R485JPBB

R485-Type Lightwave Receiver with Clock Recovery for 2.488 Gb/s Applications

TriQuint Semiconductor 

Data Sheet

March 2003

R485-Type Lightwave Receiver with Clock Recovery

for 2.488 Gb/s Applications

PWB Layout Guidelines

s The data and clock outputs are designed to drive 50 Ω loads.

s Clock and data output traces must be controlled-impedance lines and the termination impedance must match

the line impedance. Avoid 90° bends in the traces. Paired lines (i.e., DATA and DATA) must be equal in length.

s Data and clock output lines should be as short and straight as possible and should be shielded from noise

sources to prevent noise from feeding back into the receiver.

s Use high-quality multilayer printed-wiring boards. A ground plane should occupy the area directly beneath the

receiver.

4, 7, 9, 12,

14—17, 19, 20

8, 22

VCC

0.1 µF

NOTE 2

0.1 µF

0.1 µF

1 NIC

3 LOS (FLAG)

23 OILV

CLOCK 5

CLOCK 6

DATA 10

DATA 11

1 µH

+

2.2 µF

+5 V

15 µF

50 Ω TRANSMISSION

LINE (4X)

0.1 µF

NOTE 1

50 Ω

1-934(C)e

Note 1: Data and clock outputs must be ac-coupled on customer board. Use a 0.1 µF chip capacitor with a low ESR. For optimum receiver per-

formance, all four outputs must be terminated in equivalent loads, even if some of the outputs are not being used.

Note 2: The 0.1 µF VCC power supply bypass capacitors should be high-quality, low ESR chip capacitors that are located as close as possible

to the appropriate power supply leads and should provide a low inductance path to the ground plane.

Figure 4. Biasing and Interfacing to the R485-Type 2.5 Gb/s Receiver

For additional information and latest specifications, see our website: www.triquint.com

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