S24163P2.7 Просмотр технического описания (PDF) - Summit Microelectronics

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S24163P2.7

Precision RESET Controller with 16K I2C Memory

Summit Microelectronics 

S24163

SCL from

Master

1

Start

Data Output Condition

from

Transmitter

8

9

tAA

Data Output

from

Receiver

tAA ACKnowledge

FIGURE 4. ACKNOWLEDGE RESPONSE FROM RECEIVER

2014 ILL6 1.0

Input Data Protocol

One data bit is transferred during each clock pulse. The

data on the SDA line must remain stable during clock

HIGH time, because changes on the data line while SCL

is HIGH will be interpreted as start or stop condition (See

Figure 2).

START and STOP Conditions

When both the data and clock lines are HIGH, the bus is

said to be not busy. A HIGH-to-LOW transition on the data

line, while the clock is HIGH, is defined as the “START”

condition. A LOW-to-HIGH transition on the data line, while

the clock is HIGH, is defined as the “STOP” condition (See

Figure 3).

DEVICE OPERATION

The S24163 is a 16,384-bit serial E2PROM. The device

supports the I2C bidirectional data transmission protocol.

The protocol defines any device that sends data onto the

bus as a “transmitter” and any device which receives data

as a “receiver.” The device controlling data transmission

is called the “master” and the controlled device is called

the “slave.” Since it never initiates any data transfers the

S24163 is always a “slave” device.

In the READ mode the S24163 transmits eight bits of data,

then releases the SDA line, and monitors the line for an

ACKnowledge signal. If an ACKnowledge is detected,

and no STOP condition is generated by the master, the

S24163 will continue to transmit data. If an ACKnowledge is

not detected the S24163 will terminate further data transmis-

sions and await a STOP condition before returning to the

standby power mode.

Device Addressing

Following a start condition the master must output the

address of the slave it is accessing. The most significant

four bits of the slave address are the device type identifier

(see figure 5). For the S24163 this is fixed as 1010[BHEX].

Word Address

The next three bits of the slave address are an extension

of the array’s address and are concatenated with the eight

bits of address in the word address field, providing direct

access to the 2,048 X 8 array.

Read/Write Bit

The last bit of the data stream defines the operation to be

performed. When set to “1” a read operation is selected;

when set to “0” a write operation is selected.

Acknowledge (ACK)

Acknowledge is a software convention used to indicate

successful data transfers. The transmitting device, either

the master or the slave, will release the bus after transmit-

ting eight bits. During the ninth clock cycle, the receiver

will pull the SDA line LOW to ACKnowledge that it

received the eight bits of data (See Figure 4).

The S24163 will respond with an ACKnowledge after

recognition of a START condition and its slave address

byte. If both the device and a write operation are selected,

the S24163 will respond with an ACKnowledge after the

receipt of each subsequent 8-bit word.

DEVICE

IDENTIFIER

HIGH ORDER

WORD ADDRESS

1 0 1 0 A10 A9 A8 R/W

2014 ILL7 1.0

FIGURE 5. SLAVE ADDRESS BYTE

2014 2.0 3/21/00

4

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