M5M51016RT-10VL-I Просмотр технического описания (PDF) - MITSUBISHI ELECTRIC

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M5M51016RT-10VL-I

1048576-BIT (65536-WORD BY 16-BIT) CMOS STATIC RAM

MITSUBISHI ELECTRIC  

Write cycle ( BC control mode)

A0~15

BC1 and/or BC2

9 Jul ,1997

MITSUBISHI LSIs

M5M51016BTP,RT-10VL-I,

-10VLL-I

1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM

tCW

tsu (A)

tsu (BC1) or

tsu (BC2)

trec (W)

CS

(Note 3)

(Note 5)

W

(Note 3)

DQ1~16

Write cycle (CS control mode)

A0~15

(Note 4)

tsu (D)

th (D)

DATA IN

STABLE

tCW

(Note 3)

(Note 3)

BC1 and/or BC2

CS

(Note 3)

tsu (A)

tsu (CS)

trec (W)

(Note 3)

W

DQ1~16

(Note 5)

(Note 3)

(Note 4)

tsu (D)

th (D)

DATA IN

STABLE

(Note 3)

Note 3: Hatching indicates the state is "don't care".

4: Writing is executed while CS high overlaps BC1 and/or BC2 low and W low.

5: When the falling edge of W is simultaneously or prior to the falling edge of BC1 and/or BC2 or rising edge of CS, the outputs are

maintained in the high impedance state.

6: Don't apply inverted phase signal externally when DQ pin is output mode.

MITSUBISHI

ELECTRIC

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